• 한국정보통신학회논문지
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• 제10권3호
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• pp.479-485
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• 2006

이중게이트 MOSFET는 스케일링 이론을 확장하고 단채널효과를 제어 할 수 있는 소자로서 각광을 받고 있다. 단 채널효과를 제어하기 위하여 저도핑 초박막 채널폭을 가진 이중게이트 MOSFET의 경우, 20nm이하까지 스케일링이 가능한 것으로 알려지고 있다. 이 논문에서 는 20m이하까지 스켈링된 이중게이트 MOSFET소자에 대한 분석학석 전송모델을 제시하고자 한다. 이 모델을 이용하여 서브문턱스윙(Subthreshold swing), 문턱전압변화(Threshold voltage rolloff) 드레인유기장벽저하(Drain induced barrier lowering)와 같은 단채널효과를 분석하고자 한다. 제안된 모델은 열방출 및 터널링에 의한 전송효과를 포함하고 있으며 이차원 포아슨방정식의 근사해를 이용하여 포텐셜 분포를 구하였다. 또한 터널링 효과는 Wentzel-Kramers-Brillouin 근사를 이 용하였다. 이 모델을 사용하여 초박막 게이트산화막 및 채널폭을 가진 5-20nm 채널길이의 이중게이트 MOSFET에 대한 서브문턱영역의 전송특성을 해석하였다. 또한 이 모델의 결과값을 이차원 수치해석학적 모델값과 비교하였으며 게이트길이, 채널두께 및 게이트산화막 두께에 대한 관계를 구하기 위하여 사용하였다.

• 한국자기학회지
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• 제15권4호
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• pp.231-235
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• 2005

Al에 Zr과 Nb 또는 Zr과 Ti을 첨가한 삼원계 산화층을 절연층으로 사용한 자기터널접합(Magnetic Tunnel Junction, MTJ)에서, 각 원소의 비율에 따른 자기적 특성과 절연층의 미세구조 특성을 연구하였다. $(ZrNb)_{0.1}Al_{0.9}$ 및 $(ZrTi)_{0.1}Al_{0.9}$ 삼원계 산화 절연층을 가진 자기터널접합의 자기저항비는 Nb, 또는 Ti과 Zr의 첨가 비율이 1 : 1에 가까워질수록 낮아졌으며, Zr과 비교해 Nb 또는 Ti의 첨가량이 많아질수록 자기터널접합의 저항이 감소하였다. 이는 ZrNbAl, ZrTiAl 삼원계 합금 박막은 비정질인 ZrAl 이원계 합금박막과는 달리 다결정체로서 불균일한 산화 절연층을 형성하여 자기저항 및 전기적 특성을 감소시키는 역할을 하기 때문이다. 그러나 삼원계 산화 절연층의 경우 이원계 경우보다 낮은 터널 저항을 특성을 나타내었으며 이는 Nb 또는 Ti이 벤드갭 내에 국부적 에너지 준위를 만들어 에너지 장벽이 감소된 효과로 추측된다.

• Bulletin of the Korean Chemical Society
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• 제35권2호
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• pp.494-500
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• 2014

Indium-doped zinc oxide nanocrystals (IZO NCs), capped with stearic acid (SA) of different sizes, were synthesized using a hot injection method in a noncoordinating solvent 1-octadecene (ODE). The ligand exchange process was employed to modify the surface of IZO NCs by replacing the longer-chain ligand of stearic acid with the shorter-chain ligand of butylamine (BA). It should be noted that the ligand-exchange percentage was observed to be 75%. The change of particle size, morphology, and crystal structures were obtained using a field emission scanning electron microscope (FE-SEM) and X-ray diffraction pattern results. In our study, the 5 nm and 10 nm IZO NCs capped with stearic acid (SA-IZO) were ligand-exchanged with butylamine (BA), and were then spin-coated on a thermal oxide ($SiO_2$) gate insulator to fabricate a thin film transistor (TFT) device. The films were then annealed at various temperatures: $350^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, and $600^{\circ}C$. All samples showed semiconducting behavior and exhibited n-channel TFT. Curing temperature dependent on mobility was observed. Interestingly, mobility decreases with the increasing size of NCs from 5 to 10 nm. Miller-Abrahams hopping formalism was employed to explain the hopping mechanism insight our IZO NC films. By focusing on the effect of size, different curing temperatures, electron coupling, tunneling rate, and inter-NC separation, we found that the decrease in electron mobility for larger NCs was due to smaller electronic coupling.

• 한국자기학회지
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• 제16권2호
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• pp.136-139
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• 2006

자기터널접합은 일반적으로 $250^{\circ}C$ 이상의 온도에서 터널자기저항비의 저하가 발생하는데 이는 반강자성체로 사용된 IrMn 중 Mn이 강자성체인 CoFe 및 터널배리어로의 내부확산에 기인한다. 자기터널접합의 열적 안정성을 향상시키기 위하여 나노산화층을 삽입하여 Mn의 확산을 제어하였다. CoNbZr 4/CoFe 10/IrMn 7.5/CoFe 3/터널배리어/CoFe 3/CoNbZr 2(nm)와 같은 자기터널접합을 기본구조로 하여 각각의 층에 나노산화층을 삽입하여 열적안정성 및 전자기적 특성을 비교 분석 하였다. 나노산화층의 삽입에 의해 터널자기저항비, 자기터널접합의 표면 평활도 및 열적안정성이 향상되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.126-126
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• 2016

Understanding adsorption behavior organic molecules at oxide surfaces is very important for the application of organic-inorganic hybrid materials. Recently, monoethanolamine (MEA) adsorbed on $TiO_2$ surface has received great interests because it can lower the work function of $TiO_2$ in photo-electronic devices such as OLED and solar cells. In this study, we investigated the role of surface defects in adsorption behaviors of MEA at the rutile $TiO_2$ (110) surface by combined study of scanning tunneling microscopy and density functional theory calculations. Our results revealed that oxygen vacancy is the most stable adsorption site for MEA on $TiO_2$ (110) surface at low coverage. As coverage increases, the oxygen vacancies are occupied with the molecules and MEA molecules start to adsorb at Ti rows at higher coverages. Our results show that the defects at oxide surfaces and the intermolecular interactions are important factors for determining stable adsorption structure of MEA at $TiO_2$ (110) surfaces.

• 한국정보통신학회논문지
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• 제10권9호
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• pp.1648-1653
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• 2006

이 연구에서는 해석학적 전류-전압 모델을 이용하여 DGMOSFET(Double Gate MOSFET)의 전송특성을 분석하였다. MOSFET의 게이트길이가 100nm이하로 작아지면 산화막두께가 1.5m이하로 작아져야만하고 채널의 도핑이 매우 증가하기 때문에 소자의 문턱전압변화, 누설전류의 증가 등 다양한 문제가 발생하게 된다 이러한 문제를 조사하기 위하여 해석학적 전류-전압 모델을 이용하여 소자의 크기를 변화시키면서 전류-전압특성을 조사하였다 소자의 크기를 변화시키면서 해석학적 전류-전압 모델의 타당성을 조사하였으며 온도 변화에 대한 특성도 비교 분석하였다. 게이트 전압이 2V에서 77K의 전류-전압 특성이 실온에서 보다 우수하다는 것을 알 수 있었다.

• 전자공학회논문지D
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• 제34D권9호
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• pp.56-63
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• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• 한국전기전자재료학회논문지
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• 제14권8호
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• pp.688-693
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• 2001

A series of Fe/CeO$_2$/Fe$_{75}$Co$_{25}$ tunnel junctions (Magnetic Tunnel Junction, MTJ) having CeO$_2$ barrier layers from 30 to 90$\AA$ in thickness were prepared by ion beam sputtering (IBS) method. In order to compare the properties of MTJs, Fe/Al oxide/Fe-Co tunnel junctions were also prepared. Some junctions with a CeO$_2$ barrier layer showed the ferromagnetic tunneling effect and the highest MR ratio at room temperature was 5%. The electric resistance of junctions with a CeO$_2$ barrier layer was higher that that of junctions with an Al oxide barrier. On the other hand, The interface analysis of the Fe/CeO$_2$ bilayer was conducted by means of X-ray photoelectron spectroscopy (XPS). It was found that CeO$_2$ was decomposed to Ce and $O_2$ during sputtering, and Fe was oxidized with these decomposed $O_2$ molecules. The reduction of both electric resistance and MR ratio may be associated with the decomposed Ce in the barrier layer.r.r.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.75-78
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• 1998

The SONOSFET Shows low operation voltage, high cell density, anti good endurance due to modified Fowler-Nordheim tunneling as memory charge injection method. In this paper, therefore, the NOR-type Flash EEPROM composed of SONOSFET, which has fast lead operation speed and Random Access characteristics, is proposed. An 8${\times}$8 bit NOR-type SONOSFET Flash EEPROM had been designed and its electrical characteristics were verified. Read/Write/Erase operations of it were verified with the spice parameters of SONOSFETs which had Oxide-Nitride-Oxide thickness of 65${\AA}$-165${\AA}$-35${\AA}$ and that of scaled down as 33${\AA}$-53${\AA}$-22${\AA}$, respectively. When the memory window of the scaled-down SONOSFET with 8V operation was similar to that of the SONOSFET with 13V operation, the Read operation delay times of the scaled-down SONOSFET were 25.4ns at erase state and 32.6ns at program state, respectively, and those of the SONOSFET were 23.5ns at erase state and 28.2ns at program state, respectively.