• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.29-32
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• 1998

The low level leakage currents in silicon oxides were investigated. The low level leakage currents were composed of a transient component and a do component. The transient component was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The do component was caused by trap assisted tunneling completely through the oxide. The low level leakage current was proportional to the number of traps generated in the oxides. The low level leakage current may be a trap charging and discharging current. The low level leakage current will affect data retention in EEPROM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.263-266
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• 1999

Electrolunlinescent devices based on conjugated polymer emitting materials have been much attracted possible applications for multicolor flat panel display, since the conjugated polymers have a small band gap emitting obtained at a low driving voltage. In this paper, we fabricated the single layer EL device using poly(3-hexylthiophene) as emitting material Electroluminescence(EL) and I-V-L characteristics of indium-tin-oxide[ITO]P3HT/AI device with a various thickness were investigated. It was demonstrate that the I-V characteristics depend, not the voltage but the electric- field strength, The current is dependent on the electric filed and not on the applied voltage, indicating that the carriers are injected by a tunneling process. In the device, the barrier to hole injection is only 0.5eV and the barrier to electron injection is 1.5eV.

• Journal of the Korean Ceramic Society
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• v.54 no.3
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• pp.257-260
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• 2017

In this work, we present a facile one-pot synthesis of a multilayer-structured platy alumina/few-layer graphene nanocomposite by planetary milling and hot pressing. The sintered composites have electrical conductivity exhibiting percolation behavior (threshold ~ 0.75 vol.%), which is much lower than graphene oxide/ceramic composites (> 3.0 vol.%). The conductivity data are well-described by the percolation theory, and the fitted exponent values are estimated to be 1.65 and 0.93 for t and q, respectively. The t and q values show conduction mechanisms intermediate between 2D- and 3D, which originates from quantum tunneling between nearest neighbored graphenes.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.40-40
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• 2010

Employing synchrotron radiation based photoemission spectroscopy (PES) and scanning tunneling microscopy (STM), our group have investigated Si surfaces, various graphenes and molecular nanolayers. In this talk, I introduce recent results on the surface related systems. All experiments have been performed at the surface science beamlines, 3A2 and 7B1, in Pohang Accelerator Laboratory, where high resolution PES (HRPES) and angle resolved PES (ARPES) are available. Metals or molecules are adsorbed and sometimes extreme ultraviolet is irradiated onto surfaces to give them special functions. I show several examples for surface functionalzation and how to characterize solid surface using the analysis techniques. In particular, lots of ARPES and STM data are provided from graphenes, a strong candidate for replacing Si and conducting oxide currently used in many electronic and optical devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.253-253
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• 2010

유리 기판 상에 시스템 온 패널과 같은 차세대 디스플레이 구현과 평판형 디스플레이의 문제점 해결을 위하여 비휘발성 메모리 소자 등의 전자 소자 집적화와 빠른 구동 속도를 가진 박막트랜지스터가 요구된다. 본 논문에서는 비휘발성 메모리 소자에서 MONOnS 각 layer층의 두께 따른 특성에 대한 연구를 진행하였다. 실험은 ONO 구조를 12.5nm/35nm/2.7nm, 12.5nm/20nm/2.3nm, 8.5nm/10nm/2.3nm, 6.5nm/10nm/1.9nm 의 두께로 증착하였다. ${\Delta}VFB$, Retention time, capacitance을 측정하여 oxide/Nitride/Oxynitride 층의 두께 변화를 통해 최적화된 tunneling layer와 charge storage layer, 그리고 blocking layer의 두께를 알 수 있다.

• Korean Journal of Materials Research
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• v.2 no.4
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• pp.285-292
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• 1992

Ultrathin(8nm) oxynitride (SiOxNy) film have been formed on Si(100) by rapid thermal processing(RTP) in $O_2$and $N_2$O as reactants. Compared with conventional furnace $O_2$ oxide, the oxynitride dielectrics shows better characteristics of I-V and TDDB, and less flat-band voltage shift. The oxynitride has a behavior of Fowler-Nordheim tunneling in the region of V 〉${\varphi}_0$ simialr to pure Si$O_2$oxide. The relative dielectric constant of oxynitride is higher than that of conventional pure oxide. Excellent diffusion harrier property to dopant(B$F_2$) is also observed. Nitrogen depth profiles by SIMS, AES, and XPS show nitrogen pile - up at Si$O_2$/Si interface, which can explain the improved properties of oxynitride dielectrics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• Bulletin of the Korean Chemical Society
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• v.25 no.12
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• pp.1822-1828
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• 2004

Electrochemical, in situ electrochemical scanning tunneling microscope (EC-STM), and attenuated total reflectance-FTIR (ATR-FTIR) spectroscopic methods were employed to investigate the preparation of atomically flat Si(111)-H surface in ammonium fluoride solutions. Electrochemical properties of atomically flat Si(111)-H surface were characterized by anodic oxidation and cathodic hydrogen evolution with the open circuit potential (OCP) of ca. -0.4 V in concentrated ammonium fluoride solutions. As soon as the natural oxide-covered Si(111) electrode was immersed in fluoride solutions, OCP quickly shifted to near -1 V, which was more negative than the flat band potential of silicon surface, indicating that the surface silicon oxide had to be dissolved into the solution. OCP changed to become less negative as the oxide layer was being removed from the silicon surface. In situ EC-STM data showed that the surface was changed from the initial oxidecovered silicon to atomically rough hydrogen-terminated surface and then to atomically flat hydrogenterminated surface as the OCP moved toward less negative potentials. The atomically flat Si(111)-H structure was confirmed by in situ EC-STM and ATR-FTIR data. The dependence of atomically flat Si(111)-H terrace on mis-cut angle was investigated by STM, and the results agreed with those anticipated by calculation. Further, the stability of Si(111)-H was checked by STM in ambient laboratory conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.