• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.44-47
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• 1991

Electron injection and memory retention chracteristics of the MNOS devices with thin oxide layer of 23${\AA}$ thick and silicon nitride layer of 1000${\AA}$ thick which are fabricated for this experiment. As a result, pulse amplitude increase oxide current is dominated in linearly increasing region of $\Delta$V$\_$FB/the decreasing region after saturation was due to the increased silicon nirtide current. In low pulse ampiltude $\Delta$V$\_$FB/ is not variated on temperature, but as temperature and pulse amplitude increase. $\Delta$V$\_$FB/ is decreased after saturation. And the decay rate during 10$^4$sec after electron injection was ohiefly dominated by the back tunneling of emission from memory trap to silicon. Memory retention characteristics in V$\_$FB/ stage was better than that of OV retention regardless of injection conditions.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of Welding and Joining
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• v.32 no.1
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• pp.108-111
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• 2014

Low arc weldability of aluminum alloy is enhanced by applying variable polarity TIG and the result is theoretically investigated to figure out the mechanism. Conventionally, it is well known fact that DCEP (reverse polarity) arc is effective on aluminum welding. The reason is due to oxide layer removal by plasma ion bombardment and therefore it is named as cleaning effect. Another fact of polarity characteristic is that DCEN shows higher heat input efficiency therefore conventional variable polarity arc used to apply DCEP portion as small as possible. However, higher DCEP portion shows bigger weldment in this research and it is explained by adopting a theory of arc concentration on oxide layer with tunneling effect which was not clearly mentioned before in several variable polarity TIG welding research. Disagreement between variable polarity TIG welding result and conventional arc polarity theory is rationally explained for the first time with help of electron emission theory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.59-63
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• 2015

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1149-1154
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• 2014

To observe the tunneling phenomenon of oxide semiconductor transistor, The Indium-gallum-zinc-oxide thin film transistors deposited on SiOC as a gate insulator was prepared. The interface characteristics between a dielectric and channel were changed in according to the properties of SiOC dielectric materials. The transfer characteristics of a drain-source current ($I_{DS}$) and gate-source voltage ($V_{GS}$) showed the ambipolar or unipolar features according to the Schottky or Ohmic contacts. The ambipolar transfer characteristics was obtained at a transistor with Schottky contact in a range of ${\pm}1V$ bias voltage. However, the unipolar transfer characteristics was shown in a transistor with Ohmic contact by the electron trapping conduction. Moreover, it was improved the on/off switching in a ambipolar transistor by the tunneling phenomenon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.415-416
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• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

• Journal of information and communication convergence engineering
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• v.16 no.1
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• pp.43-47
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• 2018

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

• Journal of Electrochemical Science and Technology
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• v.11 no.4
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• pp.330-335
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• 2020

Silicon surface nanostructures, which can be easily prepared by electrochemical etching, have attracted considerable attention because of its useful physical properties that facilitate application in diverse fields. In this work, electrochemical and electrochemical-scanning tunneling microscopic (EC-STM) techniques were employed to study the evolution of surface morphology during the electrochemical etching of Si(111)-H in a fluoride solution. The results exhibited that silicon oxide of the Si(111) surface was entirely stripped and then the surface became hydrogen terminated, atomically flat, and anisotropic in the fluoride solution during chemical etching. At the potential more negative than the flat band one, the surface had a tendency to be eroded very slowly, whereas the steps of the terrace were not only etched quickly but the triangular pits also deepened on anodic potentials. These results provided information on the conditions required for the preparation of porous nanostructures on the Si(111) surface, which may be applicable for sensor (or device) preparation (Nanotechnology and Functional Materials for Engineers, Elsevier 2017, pp. 67-91).

• Journal of Magnetics
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• v.10 no.2
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• pp.66-70
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• 2005

The junction properties between the ferromagnet (FM) and two-dimensional electron gas (2DEG) system are crucial to develop spin electronic devices. Two types of 2DEG layer, InAs and GaAs channel heterostructures, are fabricated to compare the junction properties of the two systems. InAs-based 2DEG layer with low trans-mission barrier contacts FM and shows ohmic behavior. GaAs-based 2DEG layer with $Al_2O_3$ tunneling layer is also prepared. During heat treatment at the furnace, arsenic gas was evaporated and top AlAs layer was converted to aluminum oxide layer. This new method of forming spin injection barrier on 2DEG system is very efficient to obtain tunneling behavior. In the potentiometric measurement, spin-orbit coupling of 2DEG layer is observed in the interface between FM and InAs channel 2DEG layers, which proves the efficient junction property of spin injection barrier.