• 전기의세계
• /
• v.27 no.3
• /
• pp.31-35
• /
• 1978

In this paper, in order to clarify the mature of traps in polymer, the thermally stimulated current (TSC) measurements were mad on high density polyethylene by changing the condition of the high-field treatment such as the strength of the field (Fe), the treatment time (te) and the heating rate (.betha.). In addition, the TSC measured from the HDPE was compared with that from LDPE having different crystallinity. The obtained results can suggest that the trapping proceeds during the high-field treatment and the trap associated with the peak P$_{2}$ may have the closed relation to drystallinity and the release of trapped charge is enhanced by the molecular motion.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1942-1943
• /
• 2007

전력 계통에서는 순간적인 고장을 제거하고 양질의 전력공급을 지속시키기 위해 재폐로가 사용된다. 계통에서 고장검출 이후 차단기가 개방 되면, 전송 선로에 포획전하가 발생하여 높은 잔류 전압을 발생 시키고, 이러한 포획 전하는 선로의 재폐로시 과전압, 과전류를 발생시킨다. 재폐로시 포획 전하에 의한 과전압은 pre-insertion 저항을 삽입함으로서 경감시킬 수 있다. 본 논문에서는 이러한 포획 전하에 의한 영향을 EMTP를 통하여 분석하였다.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1045-1048
• /
• 2003

In this paper, we studied plasma damage of MIS capacitor with $Al_2$O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$O$_3$/Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.37-40
• /
• 2004

SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.329-332
• /
• 2022

In this paper, retention characteristics of lateral charge migration according to parameters of 3D NAND flash memory to which ferroelectric (HfO₂) structure is applied and ∆V_th were analyzed. The larger the P_s, the greater maximum polarization possible in ferroelectric during Programming. Therefore, the initial V_th increases by about 1.04V difference at P_s 70µC/cm² than at P_s 25µC/cm². Also, electrons trapped after the Program operation causes lateral charge migration over time. Since ferroelectric maintains polarization without applying voltage to the gate after Programming, regardless of P_s value, polarization increases as P_r increases and the ∆V_th due to lateral charge migration becomes smaller by about 1.54V difference at P_r 50µC/cm² than P_r 5µC/cm².

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.9
• /
• pp.1771-1777
• /
• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.5
• /
• pp.46-51
• /
• 1989

The degradation phenomena induced by hot-carrier injection was studied from the shift of threshold voltage and subthreshold current curve in LDD NMOSFET degraded under different DC stress-biases. Threshold voltage shift ${Delta}V_{tex}$ defined in saturation region was separated into contri butions due to trapped oxide charge $V_{ot}$ and interface traps ${Delta}V_{it}$ generated from midgap to threshold voltage. Under th positive stress electric field (TEX>$V_g>V_d$) condition, the shift of threshold voltage was attributed to the electrons traped ar gate oxide but subthreshold swing was not negative stress electric field ($V_g) condition, holes seems to be injected positive charges so threshold voltage and subthreshold swing were increased.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.5
• /
• pp.2089-2098
• /
• 2015

With the continuous development in insulation of electrical equipment design, the reliability of the system has been enhanced. However, in the manufacturing process and during operation under continues stresses introduce local defects, such as voids between interfaces that can responsible to occurrence of partial discharge (PD), electric field distortion and accumulation of charges. These defects may lead to localize corrosion and material degradation of insulation system, and a serious threat to the equipment. A model of three layers of PI film with air gap is presented to understand the influence of interface and voids on exploitation conditions such as strong electrical field, PD activity and charge movement. The analytical analysis, and experimental results are good agreement and show that the lose contact between interfaces accumulate more residual charges and in consequences increase the electric field intensity and accelerates internal discharges. These residual charges are trapped charges, injected by the electrodes has often same polarity, so the electric field in cavities increases significantly and thus partial discharge inception voltage (PDIV) decreases. Contrary, number of PD discharge quantity increases due to interface. Interfacial polarization effect has opposite impact on electric field and PDIV as compare to void.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.2
• /
• pp.83-88
• /
• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• The Korean Journal of Ceramics
• /
• v.6 no.3
• /
• pp.267-271
• /
• 2000

The influence of photoexcited nonequilibrium carriers on domain switching and photovoltaic current was investigated in two kinds of poled La-modified PbTiO$_3$ferroelectric ceramics, (Pb$_{0.85}$La$_{0.15}$)TiO$_3$and (Pb$_{0.76}$La$_{0.24}$)TiO$_3$, under illumination in the absence of external electric field. Both photovoltaic current and cumulative AE event counts increased with illumination time. The observed nonsteady-state photovoltaic current could be explained on the basis of the cycles of a series of physical events consisting the establishment of space charge field by photoexcited carriers trapped at the grain boundaries, the photoinduced domain switching, and the increase in the remanent polarization. An analysis of energy distribution of the observed AE signals also revealed that the space charge field in (Pb$_{0.85}$La$_{0.15}$)TiO$_3$allowed both 18$0^{\circ}C$ and 90$^{\circ}$domains to be switched during illumination.