• 한국유기농업학회지
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• 제19권spc호
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• pp.13-16
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• 2011

The occurrence of major pest infestation was compared between conventional tea plantation and organic tea plantation at Sulloc tea garden in Dosun-dong, Seogwipo-si, Jeju-do from 2002 to 2009. Tetranychus kanzawai was observed a lot in the second year, but it waned from late June. There was not much difference between conventional farming and organic farming in terms of pest density. Empoasca onukii was infested in the second year of organic farming compared with conventional farming, which highlighted the fact that second year of organic farming requires a special care. Scirotothrips dorsalis was highly dense in the second and third year of conventional farming, but its occurrence was lowered when the farming technique was shifted to organic farming. The number of Homona magnanima peaked 4 times each year. In 2008, the first year of organic farming, saw high occurrence of 771.2 per trap per year. In 2009, the second year, the population per trap dropped to 80, showing a great variance depending on year. The occurrence of Caloptilia theivora peaked 5 times annually. In 2008, the first year of organic farming, an average of 2,779 pests per trap was found, and in the following year, 4,143 pests were observed. It showed that density rose in organic growing period.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• 전기전자학회논문지
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• 제27권3호
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• pp.220-224
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• 2023

로우 해머는 특정 행(row)에 연속적으로 액세스할 때 인접한 행에서 비트 플립이 발생하는 현상으로 데이터 손상과 보안 문제, 컴퓨팅 성능 저하를 야기한다. 본 논문은 2ynm DRAM에서 TCAD 시뮬레이션을 통해 로우 해머의 원인과 대응 방법을 분석한다. 실험에서는 트랩의 파라미터와 소자의 구조를 변화시키면서 로우 해머 현상을 재현하고, 트랩 밀도, 온도. 액티브 위스 등과의 관계를 분석한다. 실험 결과, 트랩 파라미터와 소자 구조의 변화는 ΔV_cap/pulse에 직접적인 영향을 미치는 것을 확인하였다. 이를 통해 로우 해머에 대한 근본적인 이해와 대응 방안 모색이 가능하고 DRAM의 안정성과 보안을 향상시키는데 기여할 수 있다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.155-156
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• 2000

We propose a new in-situ fluorine passivation of poly-Si TFTs by excimer laser annealing to reduce the trap density and improve the reliability significantly. This improvement is due to the formation of stronger Si-F bonds than Si-H bonds which passivate the trap states.

• Journal of Radiation Protection and Research
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• 제34권4호
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• pp.155-164
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• 2009

In this paper, we used computerized glow curve deconvolution (CGCD) software with several models for the simulation of a TL glow curve which was used for analysis. By using the general approximation plus model, parameters values of the glow curve were analyzed and compared with the other models parameters (general approximation, mixed order kinetics, general order kinetics). The LiF:Mg,Cu,Si and the LiF:Mg,Cu,P material were used for the glow curve analysis. And we based on figure of merits (FOM) which was the goodness of the fitting that was monitored through the value between analysis model and TLD materials. The ideal value of FOM is 0 which represents a perfect fit. The main glow peak makes the most effect of radiation dose assessment of TLD materials. The main peak of the LiF:Mg,Cu,Si materials has a intensity rate 80.76% of the whole TL glow intensity, and that of LiF:Mg,Cu,P materials has a intensity rate 68.07% of the whole TL glow intensity. The activation energy of LiF:Mg,Cu,Si was analyzed as 2.39 eV by result of the general approximation plus(GAP) model. In the case of mixed order kinetics (MOK), the activation energy was analyzed as 2.29 eV. The activation energy was analyzed as 2.38 eV by the general order kinetics (GOK) model. In the case of LiF:Mg,Cu,P TLD, the activation energy was analyzed as 2.39 eV by result of the GAP model. In the case of MOK, the activation energy was analyzed as 2.55 eV. The activation energy was analyzed as 2.51 eV by the GOK model. The R value means different ratio of retrapping-recombination. The R value of LiF:Mg,Cu,Si TLD main peak analyzed as $1.12\times10^{-6}$ and $\alpha$ value analyzed as $1.0\times10^{-3}$. The R of LiF:Mg,Cu,P TLD analyzed as $7.91\times10^{-4}$, the $\alpha$ value means different ratio of initial thermally trapped electron density-initial trapped electron density (include thermally disconnected trap electrons density). The $\alpha$ value was analyzed as $9.17\times10^{-1}$ which was the difference from LiF:Mg,Cu,Si TLD. The deep trap electron density of LiF:Mg,Cu,Si was higher than the deep trap electron density of LiF:Mg,Cu,P.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.16-21
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• 2015

In this study, the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET were investigated. The device employed an ICPCVD $SiO_2$ film as a gate oxide layer on which a Ni/Au gate was evaporated. The PMA process was carried out at $350^{\circ}C$ in forming gas ambient. It was found that the device instability was improved with significant reduction in interface trap density by forming gas PMA.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.334-338
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• 2006

Poly silicon TFT requires high quality dielectric film; conventional method of growing silicon dioxide needs highly hazardous chemicals such as silane. We have grown high quality dielectric film of silicon dioxide using non-hazardous chemical such as TFOS and ozone as reaction gases by APCVD. The films grown were characterized through C-V curves of MOS structures. Conventional APCVD requires high temperature processing where as in the process of current study, we developed a low temperature process. Interface trap density was substantially decreased in the silicon surface coated with the silicon dioxide film after annealing in nitrogen ambient. The interface with such low trap density could be used for poly silicon TFT fabrication with cheaper cost and potentially less hazards.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.711-714
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• 2003

In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.