• 제목/요약/키워드: trap density

검색결과 340건 처리시간 0.034초

실리콘 산화막의 트랩 밀도에 관한 연구 (A study on the Trap Density of Silicon Oxide)

  • 김동진;강창수
    • 전자공학회논문지T
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    • 제36T권1호
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    • pp.13-18
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    • 1999
  • 본 논문은 서로 두께가 다른 실리콘 산화막의 스트레스 바이어스에 의한 트랩밀도를 조사하였다. 스트레스 바이어스에 의한 트랩밀도는 인가 시간 동안의 전류와 인가 후의 전류로 구성되어 있다. 인가 시간 동안의 트랩밀도는 직류 전류로 구성되었으며 인가 후의 트랩 밀도는 계면에서 트랩의 충전과 방전에 의한 터널링에 희해 야기되었다. 스트레스 인가 동안의 트랩밀도는 산화막 두께의 한계를 평가하는데 사용되며 스트레스 인가 후의 트랩밀도는 비휘발성 기억소자의 데이터 유지 특성을 평가하는데 사용된다.

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Analysis of Interface Trap Density between Semiconductor-Gate insulator with C-V characteristics

  • Jeong, Seung-Hyeon;Kim, Se-Min;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.645-647
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    • 2008
  • In this paper, we analyzed interface trap density between pentacene and PVP and SiO2 gate dielectric by using high-low C-V characteristics. The interface trap density was $10^{13}\;cm^{-2}eV^{-1}$.

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저밀도 폴리에틸렌 일렉트렉트에 있어서 케리어의 성질과 Trap 깊이 해석에 대한 연구 (A study on the analysis of carrier properties and trap energy depth in the low-density polythylene electrets)

  • 이준웅
    • 전기의세계
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    • 제29권8호
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    • pp.511-518
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    • 1980
  • The thermostimulated discharge currents of low-density polyethylene electrets were measured versus the principal experimental variables. Several electrode types were used for the charging and discharging procedures. The results led to know the experimental conditions for the heterocharge and homocharge accumulating and decreasing. The electronic structure parameters of polyethylene such as trap level, density of traps, hopping length, mobility, trap time constants were deduced. A method for evaluating the local electric field inside the electret is proposed.

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The Stress Dependence of Trap Density in Silicon Oxide

  • Kang, C. S.
    • 대한전자공학회논문지TE
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    • 제37권2호
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    • pp.17-24
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    • 2000
  • In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

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Charge pumping method를 이용한 MOSFET소자의 Trap분포 연구

  • 김순곤;최병덕
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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    • pp.216.2-216.2
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    • 2015
  • 본 연구에서는 charge pumping method에서 사용되는 변수들의 변화를 이용하여 hot carrier stress가 MOSFET소자의 oxide내에서의 trap 분포에 어떤 영향을 미치는지에 대해서 연구하였다. trap 분포를 확인하기 위해 스트레스 전 후에 reverse bias와 주파수에 따른 trap의 양을 측정 하였다. 스트레스 전과 후에 reverse bias와 주파수가 감소할수록 trap이 증가하는 모습이 나타났고, 스트레스 후에는 전과 비교하여 전반적으로 trap의 양이 증가하였다. 또한, 스트레스 전과 후에 MOSFET소자의 trap density는 center region에서 $2.89{\times}$10^10에서 $1.64{\times}$10^10으로 감소하였고, drain region에서 $2.83{\times}$10^10에서 $5.26{\times}$10^10으로 증가한 것을 확인하였다. 이는 reverse bias와 주파수의 가변에 따라서 trap의 공간적 분포를 측정할 수 있다는 것을 의미한다.

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SiGe p-FinFET의 C-V 특성을 이용한 평균 계면 결함 밀도 추출과 Terman의 방법을 이용한 검증 (Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman's Method)

  • 김현수;서영수;신형철
    • 전자공학회논문지
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    • 제52권4호
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    • pp.56-61
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    • 2015
  • 고주파에서 이상적인 커패시턴스-전압 곡선과 결함이 존재하여 늘어진 커패시턴스-전압 곡선을 SiGe p-FinFET 시뮬레이션을 이용하여 보였다. 두 곡선이 게이트 전압 축으로 늘어진 전압 차이를 이용하여 평균적인 계면 결함 밀도를 구할 수 있었다. 또한 같은 특성을 이용하는 Terman의 방법으로 에너지에 따른 계면 결함 밀도를 추출하고, 동일한 에너지 구간에서 평균값을 구하였다. 전압 차이로 구한 평균 계면 결함 밀도를 Terman의 방법으로 구한 평균값과 비교하여, 두 방법의 결과가 거의 비슷한 평균 계면 결함 밀도를 나타낸다는 것을 검증하였다.

GaN Schottky Barrier MOSFET의 출력 전류에 대한 계면 트랩의 영향 (Interface Trap Effects on the Output Characteristics of GaN Schottky Barrier MOSFET)

  • 박병준;김한솔;함성호
    • 센서학회지
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    • 제31권4호
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    • pp.271-277
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    • 2022
  • We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the Nit distribution using TCAD simulation. As interface trap number density (Nit) increased, the threshold voltage increased while the drain current density decreased. Under Nit=5.0×1010 cm-2 condition, the threshold voltage was 3.2 V for VDS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the Nit distribution type, there was an increase in the subthreshold swing (SS) following an increase in Nit. Under U-shaped Nit distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Qf) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

안료의 표면적이 잉크물성에 미치는 영향 (Effect of Surface Area of Pigments on The Physical Properties of Printing Ink)

  • 김종래
    • 한국인쇄학회지
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    • 제14권2호
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    • pp.21-36
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    • 1996
  • With increased use of halftone dot overprints for offset color printing, it is important to study the density and ink trap of the overprints. In this research the equation to predict the density and the method to evaluate ideally the fractional ink trap are preposed. And also the halftone dot overprinting experiments of Magenta over Cyan or Cyan over Magenta under wet-on-wet or wet-on-dry overprinting using 2-color offset press show the above proposals are reasonable, and show the effect of overprinting sequence on the density and ink trap.

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The Study on the Trap Density in Thin Silicon Oxide Films

  • 강창수;김동진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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    • pp.43-46
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    • 2000
  • In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

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Effect of Orius laevigatus and Neoseiulus cucumeris on Suppression of Thrips Density on Paprika in Greenhouse in Summer

  • Lim, Y.S.;Lee, M.J.;Shin, Y.S.;Han, Y.Y.
    • 한국유기농업학회지
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    • 제19권spc호
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    • pp.214-217
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    • 2011
  • When paprika is cultivated during summer season, thrips starts to occur in the early growing season and reaches its peak in late June. In the treatment using Orius laevigatus and Neoseiulus cucumeris, natural enemies to thrips, thrips density was 87.6/trap and 51.3/trap on June 23. After Orius laevigatus and Neoseiulus cucumeris were treated twice on June 24 and July 23, the number decreased considerably. On August 23, it was 36.9/trap and 40.3/trap and from the mid August to early September thrips density remained low. Effect of Orius laevigatus and Neoseiulus cucumeris on suppression of thrips density was 35.7% and 44.6% on July 22, however, the number went up to 88.8% and 80.5% on September 3.