• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.28-34
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• 2011

In previous reports, we investigated a selective assembly method of fabricating single-walled carbon nanotubes (SWCNTs) on a silicon-dioxide ($SiO_2$) surface by using only a photolithographic process. In this paper, we have fabricated field effect transistors (FETs) with SWCNT channels by using the technique mentioned above. Also, we have electrically measured gating effects of these FETs under different source-drain voltages ($V_{SD}$). These FETs have been fabricated for sensor applications. Photoresist (PR) patterns have been made on a $SiO_2$-grown silicon (Si) substrate by using a photolithographic process. This PR-patterned substrate have been dipped into a SWCNT solution dispersed in dichlorobenzene (DCB). These PR patterns have been removed by using aceton. As a result, a selectively-assembled SWCNT channels in FET arrays have been obtained between source and drain electrodes. Finally, we have successfully fabricated 4 FET arrays based on SWCNT-channels by using our simple self-assembly technique.

• Bulletin of the Korean Chemical Society
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• v.32 no.2
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• pp.417-423
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• 2011

A series of new quinoxaline-based thiophene copolymers (PQx2T, PQx4T, and PQx6T) was synthesized via Yamamoto and Stille coupling reactions. The $M_ws$ of PQx2T, PQx4T, and PQx6T were found to be 20,000, 12,000, and 29,000, with polydispersity indices of 2.0, 1.2, and 1.1, respectively. The UV-visible absorption spectra of the polymers showed two distinct absorption peaks in the ranges 350 - 460 nm and 560 - 600 nm, which arose from the ${\pi}-{\pi}^*$ transition of oligothiophene units and intramolecular charge transfer (ICT) between a quinoxaline acceptor and thiophene donor. The HOMO levels of the polymer ranged from -5.37 to -5.17 eV and the LUMO levels ranged from -3.67 to -3.45 eV. The electrochemical bandgaps of PQx2T, PQx4T, and PQx6T were 1.70, 1.71, and 1.72 eV, respectively, thus yielding low bandgap behavior. PQx2T, PQx4T, and PQx6T had open circuit voltages of 0.58, 0.42, and 0.47 V, and short circuit current densities of 2.9, 5.29 and 9.05 mA/$cm^2$, respectively, when $PC_{71}BM$ was used as an acceptor. For the solar cells with PQx2T-PQx6T:$PC_{71}BM$ (1:3) blends, an increase in performance was observed in going from PQx2T to PQx6T. The power conversion efficiencies of PQx2T, PQx4T, and PQx6T devices were found to be 0.69%, 0.73%, and 1.80% under AM 1.5 G (100 mW/$cm^2$) illumination.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.14-18
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• 2020

This study investigates the nitrogen dioxide (NO₂) sensing characteristics of an Si MOSFET gas sensor with a tungsten trioxide (WO₃) sensing layer deposited using the sputtering method. The Si MOSFET gas sensor consists of a horizontal floating gate (FG) interdigitated with a control gate (CG). The WO₃ sensing layer is deposited on the interdigitated CG-FG of a field effect transistor(FET)-type gas sensor platform. The sensing layer is deposited with different thicknesses of the film ranging from 100 nm to 1 ㎛ by changing the deposition times during the sputtering process. The sensing characteristics of the fabricated gas sensor are measured at different NO₂ concentrations and operating temperatures. The response of the gas sensor increases as the NO₂ concentration and operating temperature increase. However, the gas sensor has an optimal performance at 180℃ considering both response and recovery speed. The response of the gas sensor increases significantly from 24% to 138% as the thickness of the sensing layer increases from 100 nm to 1 ㎛. The sputtered WO₃ film consists of a dense part and a porous part. As reported in previous work, the area of the porous part of the film increases as the thickness of the film increases. This increased porous part promotes the reaction of the sensing layer with the NO₂ gas. Consequently, the response of the gas sensor increases as the thickness of the sputtered WO₃ film increases.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.1-8
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• 2005

A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.105-111
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• 2004

In this paper, millimeter-wave high gain and broadband MHEMT cascode amplifiers were designed and fabricated. The 0.1 ${\mu}{\textrm}{m}$ InGaAs/InAlAs/GaAs Metamorphic HEMT was fabricated for cascode amplifiers. The DC characteristics of MHEMT are 640 mA/mm of drain current density, 653 mS/mm of maximum transconductance. The current gain cut-off frequency(f$_{T}$) is 173 GHz and the maximum oscillation frequency(f$_{max}$) is 271 GHz. By using the CPW transmission line, the cascode amplifier was designed the matched circuit for getting the broadband characteristics. The designed amplifier was fabricated by the MHEMT MIMIC process that was developed through this research. As the results of measurement, the 1 stage amplifier obtained 3 dB bandwidth of 37 GHz between 31.3 to 68.3 GHz. Also, this amplifier represents the S21 gain with the average 9.7 dB gain in bandwidth and the maximum gain of 11.3 dB at 40 GHz. The 2 stage amplifier has the broadband characteristics with 3 dB bandwidth of 29.5 GHz in the frequency range from 32.5 to 62.0 GHz. The 2 stage cascode amplifier represents the high gain characteristics with the average gain of 20.4 dB in bandwidth and the maximum gain of 22.3 dB at 36.5 GHz.z.z.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.12-18
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• 2008

Ag paste was employed for source and drain electrode of OTFTs and for the data metal lines of OTFT-OLED array on PC(polycarbonate) substrate. We tested two kinds of Ag-pastes such as pastes for 325 mesh and 500 mesh screen mask to examine the pattern ability and electrical performance for OTFTs. The minimum feature size was 60 ${\mu}m$ for 325 mesh screen mask and 40 ${\mu}m$ for 500 mesh screen mask. The conductivity was 60 $m{\Omega}/\square$ for 325 mesh and 133.1 $m{\Omega}/\square$ for 500 mesh. For the OTFT performance the mobility was 0.35 $cm^2/V{\cdot}sec$ and 0.12 $cm^2/V{\cdot}sec$, threshold voltage was -4.7 V and 0.9 V, respectively, and on/off current ratio was ${\sim}10^5$, for both screen masks. We applied the 500 mash Ag paste to OTFT-OLED array because of its good patterning property. The pixel was composed of two OTFTs and one capacitor and one OLED in the area of $2mm{\times}2mm$. The panel successfully worked in active mode operation even though there were a few bad pixels.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.1
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• pp.15-22
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• 2008

In this paper, we propose a numerical analysis on reversed current of distributed amplifier based on transmission line theory and proposed a theory to obtain optimum transmission line length to minimize the reversed currents by cancelling those components. The reversed current is analyzed as being simply absorbed into the terminal resistance in the conventional analysis. In the proposed analysis, however, they are designed to be cancelled by each other with opposite phase by the optimal length of the transmission lint Circuit simulation and implementation using pHEMT transistor were performed to validate the proposed theory with the cutoff frequency of 3.6 GHz. From the measurement, maximum gain of 14.5dB and minimum gain of 12.3dB were achieved In the operation band. Moreover, measured efficiency of the proposed distributed amplifier is 25.6% at 3 GHz, which is 7.6%, higher than the conventional distributed amplifier. Measured output power Is about 10.9dBm, achieving 1.7dB higher output power than the conventional one. Those improvement is thought to be based on the cancellation of refersed current.