Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Design of Low Power 16-bit ALU by Switched Capacitance Reduction

Switched Capacitance 감소를 통한 저전력 16비트 ALU 설계

  • Ryu, Beom-Seon (School of electronic and Electrical Engineering Chungbuk National Univ.) ;
  • Lee, Jung-Sok (School of electronic and Electrical Engineering Chungbuk National Univ.) ;
  • Lee, Kie-Young (School of electronic and Electrical Engineering Chungbuk National Univ.) ;
  • Cho, Tae-Won (School of electronic and Electrical Engineering Chungbuk National Univ.)
  • 유범선 (忠北大學校 電氣電子工學部) ;
  • 이중석 (忠北大學校 電氣電子工學部) ;
  • 이기영 (忠北大學校 電氣電子工學部) ;
  • 조태원 (忠北大學校 電氣電子工學部)
  • Published : 2000.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

본 논문에서는 새로운 16비트 저전력 ALU(Arithmetic Logic Unit) 구조 및 회로를 제안하여 트랜지스터 레벨로 설계, 제작 및 테스트하였다. 설계한 ALU는 16개의 명령어를 수행하며 2단계 파이프라인 구조를 가진다. 제안한 ALU는 switched capacitance를 줄이기 위해 논리연산시에는 덧셈기가 스위칭하지 않도록 하였으며, P(propagation)블록의 출력을 듀얼버스(dual bus)구조로 하였다. 또한 이와 같은 ALU구조를 위한 새로운 효율적인 P 및 G(generation)블록을 제안하였다. 그 외에 저전력 실현을 위하여 ELM덧셈기, 이중모서리 천이 플립플롭double-edge triggered flip-flop) 및 조합형 논리형태(combination of logic style)을 사용하여 ALU를 구현하였다. 모의실험결과, 제안한 구조는 기존의 구조$^{[1.2]}$에 비교하여 수행되는 산술연산의 사용횟수에 대하여 논리연산의 사용횟수가 증가할수록 전력감축의 효과가 증가하였다. 수행되는 산술연산 대 논리연산의 전형적인 비율을 7:3이라고 가정할 때, 제안한 구조는 기존 구조에 비해서 12.7%의 전력감축을 보였다. 설계한 ALU는 0.6${\mu}m$ 단일폴리, 삼중금속 CMOS 공정으로 제작하였다. 칩 테스트 결과 최대동작 주파수는 53MHz로 동작하였고 전력소모는 전원전압 3.3 V, 동작 주파수 50MHz에서 33mW를 소모하였다.

Keywords

References

  1. Carver Mead, Lynn Conway, 'Introduction to VLSI system,' Addition-wesley publishing compony, pp 150-154, 1980
  2. Abdellatif Bellaouar, Mohamed I. Elmasry, 'Low Power Digital VLSI Design,' Kluwer academic publishers, 1995
  3. 곽승호, 최병윤, 이문기, 'PDA를 위한 32비트 RISC 코어의 설계,' 한국통신학회 논문지, 제22권, 제10호, pp 2136-2149, 1997
  4. Makoto Suzuki, 'A 1.5ns 32 b CMOS ALU in Double Pass-Transistor LOgic' IEEE journal of Solid-State circuits. vol. 28, NO. 11, pp. 1145-1150, November 1993 https://doi.org/10.1109/4.245595
  5. Reto zimmermann and wolfgang fichtner 'Low power logic style : CMOS versus pass transistor Logic,' IEEE J. of Solid-state Circuit, vol. 32, no. 7, July, 1997 https://doi.org/10.1109/4.597298
  6. Anantha P. Chandrakasam, Robert W. Brodersen, 'Low Power Digital CMOS Design,' Kluwer academic publishers, 1995
  7. Jan M. Rabaey, Massoud Pedraw, 'Low Power Design Methodologies,' Kluwer academic publishers, pp 37-62, 1996
  8. T. P. Kelliher, R. M. Owens, M. J. Irwin, and T. T. Hwang, 'ELM-A Fast Addition Algorithm Discovered By a Program,' IEEE Transactions on Computers, Vol. 41, No. 9, Sep. 1992 https://doi.org/10.1109/12.165399
  9. C. Nagendra, M. J. Irwin, arel R. M. Owens, 'Area-Time-Power Tradeoffs in Parallel Adders,' IEEE Transactions on Circuits and Systems, Vol. 43, No. 10, Oct. 1996 https://doi.org/10.1109/82.539001
  10. 김문수, 유범선, 강성현, 이중석, 조태원, '하이브리드 로직 스타일을 이용한 저전력 ELM 덧셈기 설계,' 전자공학회 논문지, 제35권, C편, 제3호, pp. 389-396, 1998
  11. J. M. Wang, S. C. Fang, and W. S. Feng, 'New Efficient Designs for XOR and XNOR Functions on the Transistor level,' IEEE J. of Solid-state Circits, vol. s29, no. 7, July, 1994
  12. M. Afghahi, J. Yuan, 'Double edge-triggered D-flip-flops for High Speed CMOS Circuits,' IEEE J. of Solid-State Circuits, Vol. 26, No. 8, pp 1168-1170, 1991 https://doi.org/10.1109/4.90071
  13. R. Llopis and M. Sachdev, 'Low Power Testable Dual Edge Triggered Flip-Flop,' Digest of Technical Papers, International Symposium on Low Power Electronics and Design, pp. 341-345, 1996 https://doi.org/10.1109/LPE.1996.547536