• Journal of the Institute of Convergence Signal Processing
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• v.2 no.1
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• pp.113-118
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• 2001

In this paper, we implement modules of the MPEG-2 AAC decoder using VHDL. Tools of Huffman decoder, inverse quantizer and high-density filter bank which are necessary for the AAC decoder. We designed the high speed Huffman decoder using the method of octal tree search algorithm, and reduced computational time of filter bank using IFFT. Also, we use table of computation result for an exponential calculation of Inverse quantizer in fixed-point hardware, and reduced the size of table using linear interpolation. Modules implemented by hardware through optimization work in real time at low clock frequency are possible to reduce the system size.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.4
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• pp.305-317
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• 2020

The navigation message is composed of the information contained in the message and the structure for transmitting this information. In order to design a navigation message, considerations in terms of message content and message structure must be elicited. For designing a Korea Positioning System (KPS) navigation message, this paper explains performance indicators in terms of message structure and message content. Most of the performance analysis of GNSS navigation messages already in operation was performed only for Time-to-first-fix-Data (TTFFD). However, in the navigation message, the message content is composed of Clock-Ephemeris Data (CED) and additional information. So, this paper proposes a new performance indicator R_(Non-CED) that can be analyzed from the viewpoint of receiving additional information along with an explanation of TTFFD focusing on the CED reception time. This paper analyze the performance in terms of message structure using these two performance indicators. The message structures used for analysis are the packetized message protocol like GPS CNAV and the packetized and fixed pattern message protocol like GPS CNAV-2. From the results, it is possible to proffer how KPS navigation messages can have better performance than GPS navigation messages. And, these two performance indicators, TTFFD and R_Non-CED, can help to design the minimum TTFF required performance of KPS navigation messages.

• International conference on construction engineering and project management
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• 2013.01a
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• pp.21-27
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• 2013

Construction safety is a predominant hindrance in in-situ workflow and considered an unresolved issue. Current methods used for safety optimization and prediction, with limited exceptions, are paper-based, thus error prone, as well as time and cost ineffective. In an attempt to exploit the potential of BIM for safety, the objective of the proposed methodology is to automatically predict hazardous on-site conditions related to the route that the dozers follow during the different phases of the project. For that purpose, safety routes used by construction equipment from an origin to multiple destinations are computed using video cameras and their cycle times are calculated. The cycle times and factors; including weather and light conditions, are considered to be independent and identically distributed random variables (iid); and simulated using the Arena software. The simulation clock is set to 100 to observe the minor changes occurring due to external parameters. The validation of this technology explores the capabilities of BIM combined with simulation for enhancing productivity and improving safety conditions a-priori. Preliminary results of 262 measurements indicate that the proposed methodology has the potential to predict with 87% the location of exclusion zones. Also, the cycle time is estimated with an accuracy of 89%.

• Journal of IKEEE
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• v.20 no.4
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• pp.351-360
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• 2016

Recently, machine learning algorithms, especially deep learning-based algorithms, have been receiving attention due to its high classification performance. Among the algorithms, Convolutional Neural Network(CNN) is known to be efficient for image processing tasks used for Advanced Driver Assistance Systems(ADAS). However, it is difficult to achieve real-time processing for CNN in vehicle embedded software environment due to the repeated operations contained in each layer of CNN. In this paper, we propose a hardware accelerator which enhances the execution time of CNN by parallelizing the repeated operations such as convolution. Xilinx ZC706 evaluation board is used to verify the performance of the proposed accelerator. For $36{\times}36$ input images, the hardware execution time of CNN is 2.812ms in 100MHz clock frequency and shows that our hardware can be executed in real-time.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.736-748
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• 2003

Dynamic voltage scaling(DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded real-time systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. In this paper, we propose novel DVS algorithms for periodic hard real-time tasks based on an improved slack estimation algorithm. Unlike the existing techniques, the proposed method can be applied to most priority-driven scheduling policies. Especially, we apply the proposed slack estimation method to EDF and RM scheduling policies. The experimental results show that the DVS algorithms using the proposed slack estimation method reduce the energy consumption by 20∼40 % over the existing DVS algorithms.

• Journal of IKEEE
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• v.20 no.3
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• pp.209-219
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• 2016

SVM is a machine learning method used for image processing. It is well known for its high classification performance. We have to perform multiple MAC operations in order to use SVM for image classification. However, if the resolution of the target image or the number of classification cases increases, the execution time of SVM also increases, which makes it difficult to be performed in real-time applications. In this paper, we propose an hardware architecture which enables real-time applications using SVM classification. We used parallel architecture to simultaneously calculate MAC operations, and also designed the system for several feature extractors for compatibility. RBF kernel was used for hardware implemenation, and the exponent calculation formular included in the kernel was modified to enable fixed point modelling. Experimental results for the system, when implemented in Xilinx ZC-706 evaluation board, show that it can process 60.46 fps for $1360{\times}800$ resolution at 100MHz clock frequency.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.171-174
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• 2006

A large number of service providers in countries all over the world have established GNSS reference station networks in the last years and are using network software today to provide a correction stream to the user as a routine service. In current GNSS network processing, all the geometric related information such as ionospheric free carrier phase ambiguities from all stations and satellites, tropospheric effects, orbit errors, receiver and satellite clock errors are estimated in one centralized Kalman filter. Although this approach provides an optimal solution to the estimation problem, however, the processing time increases cubically with the number of reference stations in the network. Until now one single Personal Computer with Pentium 3.06 GHz CPU can only process data from a network consisting of no more than 50 stations in real time. In order to process data for larger networks in real time and to lower the computational load, a federated filter approach can be considered. The main benefit of this approach is that each local filter runs with reduced number of states and the computation time for the whole system increases only linearly with the number of local sensors, thus significantly reduces the computational load compared to the centralized filter approach. This paper presents the technical aspect and performance analysis of the federated filter approach. Test results show that for a network of 100 reference stations, with the centralized approach, the network processing including ionospheric modeling and network ambiguity fixing needs approximately 60 hours to process 24 hours network data in a 3.06 GHz computer, which means it is impossible to run this network in real time. With the federated filter approach, only less than 1 hour is needed, 66 times faster than the centralized filter approach. The availability and reliability of network processing remain at the same high level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.11
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• pp.1462-1467
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• 2018

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

• Journal of the korean academy of Pediatric Dentistry
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• v.44 no.1
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• pp.64-71
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• 2017

This study was designed to evaluate the age, gender, location of trauma, etiology, injury site, types of treatment, elapsed time after trauma, and arrival time of children who visited trauma center of Wonju Severance Christian Hospital. Records of a total of 841 patients who were 0 - 15 years old and received care in the period from March 2011 to October 2015 at the Trauma Center, Wonju Severance Christian Hospital were analyzed. This study showed that traumatic dental injuries were more common in boys and patients between 0 - 3 years old. Under 6 years old, fall was the most common etiology and home was the most common place of trauma. However, fall decreased, and sports and etc increased largely in etiologic factors over 6 years old. Besides, home decreased, and road and kindergarten school increased largely in the place of trauma. Etiology and location of trauma were statistically influenced by the age (p < 0.05). The most commonly affected injury sites were maxillary incisors and lips. The most patients visited trauma center between 18 - 24 o'clock (53.3%), and the least patients visited between 0 - 6 o'clock (4.6%). 51.5% of patients visited the trauma center within 1 hour of sustaining trauma, and 26.8% and 11.5% of patients visited between 1 - 2 hours and 2 - 3 hours respectively. The most common treatment of traumatic dental injuries was observation, and the second most common treatment was suture. Traumatic dental injuries in children exhibit specific epidemiological features according to children's gender, age, and other conditions. These result from combination of social, developmental, and physiologic factors.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.