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Real-Time Hardware Design of Image Quality Enhancement Algorithm using Multiple Exposure Images

다중 노출 영상을 이용한 영상의 화질 개선 알고리즘의 실시간 하드웨어 설계

  • Lee, Seungmin (Department of Electronic Engineering, Dong-A University) ;
  • Kang, Bongsoon (Department of Electronic Engineering, Dong-A University)
  • Received : 2018.07.13
  • Accepted : 2018.08.14
  • Published : 2018.11.30

Abstract

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

단일 노출 영상, 또는 다중 노출 영상을 사용하여 저조도 영상의 화질 개선 알고리즘이 수많이 연구되고 있다. 저조도 영상은 명암이 낮고, 잡음이 많아 피사체의 정보를 식별하기에 한계가 있다. 본 논문에서는 듀얼카메라로 촬영한 다중 노출 영상 2개를 이용하여 저조도 영상의 화질 개선하는 알고리즘의 하드웨어 설계를 제안한다. 제안하는 하드웨어 구조는 전달함수를 사용하여 프레임 메모리와 라인 메모리를 쓰지 않는 방식으로 실시간 처리로 설계되었다. 그리고 제안하는 하드웨어 설계는 Verilog로 설계했고, Modelsim을 사용하여 검증했다. 마지막으로 Xilinx사의 xc7z045-2ffg900을 목표 보드로 이용하여 FPGA를 구현했을 때 최대 동작 주파수 167.617MHz로 확인하였고, 영상 크기가 $1920{\times}1080$ 일 때, 소요된 총 클럭 사이클은 2,076,601이며 80.7fps로 실시간 처리가 가능하다.

Keywords

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Fig. 1 Flow chart of the proposed algorithm

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Fig. 2 Input images (a) LET image (b) SET image

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Fig. 3 Transfer function using LET image characteristics

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Fig. 4 Transfer function using SET image characteristics

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Fig. 5 Histogram of LET image

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Fig. 6 Histogram of SET image

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Fig. 7 Histogram of blended image

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Fig. 8 Result images (a) blended image (b) proposed result image

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Fig. 9 Histogram of proposed result image

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Fig. 10 Hardware block diagram

Table. 1 Summary of Xilinx Synthetic Result

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