• Title/Summary/Keyword: threshold voltage model

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Analysis of Transport Characteristics for Double Gate MOSFET using Analytical Current-Voltage Model (해석학적 전류-전압모델을 이용한 이중게이트 MOSFET의 전송특성분석)

  • Jung Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.9
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    • pp.1648-1653
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    • 2006
  • In this paper, transport characteristics have been investigated using analytical current-voltage model for double gate MOSFET(DGMOSFET). Scaling down to 100nm of gate length for MOSFET can bring about various problems such as a threshold voltage roll-off and increasing off current by tunneling since thickness of oxide is down by 1.fnm and doping concentration is increased. A current-voltage characteristics have been calculated according to changing of channel length,using analytical current-voltage relation. The analytical model has been verified by calculating I-V relation according to changing of oxide thickness and channel thickness as well as channel length. A current-voltage characteristics also have been compared and analyzed for operating temperature. When gate voltage is 2V, it is shown that a current-voltage characteristic in 77K is superior to in room temperature.

The Analysis of Breakdown Voltage for the Double-gate MOSFET Using the Gaussian Doping Distribution

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.200-204
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    • 2012
  • This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

Analysis of Flat-Band-Voltage Dependent Breakdown Voltage for 10 nm Double Gate MOSFET

  • Jung, Hakkee;Dimitrijev, Sima
    • Journal of information and communication convergence engineering
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    • v.16 no.1
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    • pp.43-47
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    • 2018
  • The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET (무접합 원통형 MOSFET에 대한 드레인 유도 장벽 감소의 SPICE 모델)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.5
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    • pp.278-282
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    • 2018
  • We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

Poly-crystalline Silicon Thin Film Transistor: a Two-dimensional Threshold Voltage Analysis using Green's Function Approach

  • Sehgal, Amit;Mangla, Tina;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.287-298
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    • 2007
  • A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

Computing-Inexpensive Matrix Model for Estimating the Threshold Voltage Variation by Workfunction Variation in High-κ/Metal-gate MOSFETs

  • Lee, Gyo Sub;Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.96-99
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    • 2014
  • In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

Simulation of do Performance and Gate Breakdown Characteristics of MgO/GaN MOSFETs (MgO/GaN MOSFETs의 dc 특성 및 Gate Breakdown 특성 Simulation)

  • Cho, Hyeon;Kim, Jin-Gon;Gila, B.P.;Lee, K.P.;Abernathy, C.R.;Pearton, S.J.;Ren, F.
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2003.11a
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    • pp.176-176
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    • 2003
  • The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

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Analysis of Effective Gate resistance characteristics in Nano-scale MOSFET for RFIC (RFIC를 위한 Nano-scale MOSFET의 Effective gate resistance 특성 분석)

  • 윤형선;임수;안정호;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.11
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    • pp.1-6
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    • 2004
  • Effective gate resistance, extracted by direct extraction method, is analyzed among various gate length, in nanoscale MOSFET for RFIC. Extracted effective gate resistance is compared to measured data and verified with simplified model. Extracted parameters are accurate to 10GHz. In the same process technology effect has a different kind of gate voltage dependency and frequency dependency compared with general effective gate resistance. Particularly, the characteristic of effective gate resistance before and after threshold voltage is noticeable. When gate voltage is about threshold voltage, effective gate resistance is abnormally high. This characteristic will be an important reference for RF MOSFET modeling using direct extraction method.

Analysis of the Drain Current in Nonuniformly Doped Channel(NUDC) MOSFET's due to Pocket Ion Implantation (포켓 이온주입으로 비균질 채널도핑을 갖는 MOSFET소자의 드레인 전류 해석)

  • Koo, Hoe-Woo;Park, Joo-Seog;Lee, Kie-Young
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.9
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    • pp.21-30
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    • 1999
  • Halo pocket implantation in MOSFETs, which is known to be an efficient method to provent the punchthrough and threshold voltage roll-off phenomena, decreases the drain current of MOSFET devices. Although the decrease of the drain current in halo structure MOSFET is usually explained in terms of the increase of the threshold voltage, more decrease in the drain current than is predicted by the increased threshold voltage has experimentally been observed. In this work, the effect of halo doping profile on the drain current degradation is investigated in terms of the field distribution along the channel. Effective mobility model of the halo MOSFETs due to pocket implantation is presented and the degradation of the mobility is shown to be effective in the further decrease of the drain current. Present model is shown to be in good agreement with experimental results.

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SPICE Parameter Extraction for the IGBT (IGBT의 SPICE 파라미터 추출)

  • 김한수;조영호;최성동;최연익;한민구
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.4
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    • pp.607-612
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    • 1994
  • The static and dynamic model of IGBT for the SPICE simulation has been successfully developed. The various circuit model parameters are extracted from the I-V and C-V characteristics of IGBT and implemented into our model. The static model of IGBT consists of the MOSFET, bipolar transistor and series resistance. The parameters to be extracted are the threshold voltage of MOSFET, current gain $\beta$ of bipolar transistor, and the series resistance. They can be extracted from the measured I-V characteristics curve. The C-V characteristics between the terminals are very important parameters to determine the turn-on and turn-off waveform. Especially, voltage dependent capacitance are polynomially approximated to obtain the exact turn-on and turn-off waveforms. The SPICE simulation results employing new model agree well with the experimental values.

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