• E2M - 전기 전자와 첨단 소재
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• 제9권8호
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• pp.813-818
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• 1996

Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$ device shows the memory switching characteristics under d.c. bias. In bulk material, a-As$_{10}$Ge$_{15}$ Te$_{75}$ switching threshold voltage (V$_{th}$) is very high (above 100 volts), but in the case of thin film, V$_{th}$ decreases to a few or ten a few volts. The characteristics of V$_{th}$ depends on the physical dimensions such as the thickness of thin film and the separation between d.c. electrodes, and the annealing conditions. The switching threshold voltage decreases exponentially with increasing annealing temperature and annealing time, but increases linearly with the thickness of thin film and exponentially with increasing the separation between d.c. electrodes. The desirable low switching threshold voltage, therefore, can be obtained by the stabilization through annealing and changing physical dimensions.imensions.sions.

• 한국전기전자재료학회논문지
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• 제26권2호
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• pp.92-97
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• 2013

In this paper the author proposes a method of implementing a numerical model for threshold voltage ($V_{th}$) shift in organic thin-film transistors (OTFTs) into SPICE tools. $V_{th}$ shift is first numerically modeled by dividing the shift into sequentially ordered groups. The model is then used to derive a simulations model which takes into simulation parameters and calculation complexity. Finally, the numerical and simulation models are implemented in AIM-SPICE. The SPICE simulation results agree well with the $V_{th}$ shift obtained from an OTFT fabricated without any optimization. The proposed method is also used to implement the stretched-exponential time dependent $V_{th}$ shift in AIM-SPICE and the results show the proposed method is applicable to various types of $V_{th}$ shifts.

• 전기전자학회논문지
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• 제28권1호
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• pp.110-115
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• 2024

본 논문은 3D NAND Flash memory에서 tapering된 O/N/O(Oxide/Nitride/Oxide) 구조와 blocking oxide를 ferroelectric material로 대체한 O/N/F(Oxide/Nitride/Ferroelectric) 구조의 V_th(Threshold Voltage) 변화량을 분석했다. Tapering 각도가 0°일 때 O/N/F 구조는 O/N/O 구조보다 저항이 작고 WL(Word-Line) 상부와 WL 하부의 V_th 변화량이 감소한다. Tapering된 3D NAND Flash memory는 WL 상부에서 WL 하부로 내려갈수록 channel 면적이 감소하며 channel 저항이 증가한다. 따라서 tapering 각도가 증가할수록 WL 상부의 V_th가 감소하고 WL 하부의 V_th는 증가한다. Tapering된 O/N/F 구조는 channel 반지름 길이와 비례하는 V_fe로 인해 WL 상부의 V_th는 O/N/O 구조보다 더 감소한다. 또한 O/N/F 구조의 WL 하부는 O/N/O 구조보다 V_th가 증가하기 때문에 tapering 각도에 따른 V_th 변화량이 O/N/O 구조보다 더 증가한다.

• 전기전자학회논문지
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• 제24권1호
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• pp.284-292
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• 2020

SiC 기반 소자는 silicon 소자 대비 1200V 이상의 고전압 환경에서 우수하게 동작하며 특히 매우 높은 온도에서 안정적인 특성을 보여준다. 따라서 최근 1700V급 UMOSFET이 전기 자동차, 항공기 등의 전력시스템의 사용을 목표로 활발하게 연구개발 되고 있다. 본 논문에서는 최근 연구되고 있는 세 종류의 1700급 UMOSFET-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), Local Floating Superjunction UMOSFET (LFS-UMOSFET)-에 대해 온도 변화(300K-600K)에 따른 전력소자에서 중요한 변수 (breakdown voltage(BV), on-resistance(R_on), threshold voltage(v_th), transconductance(g_m))의 신뢰성 특성을 비교 분석하였다. 세 소자 모두 온도 증가에 따른 BV 증가, R_on 증가, v_th 감소, g_m 감소를 확인하였다. 그러나 세 소자의 구조 차이에 따라 BV, R_on v_th, g_m 변화에 차이가 있어 그 정도 및 원인에 대해 비교 분석하였다. 모든 결과는 sentaurus TCAD을 통해 simulation 되었다.

• Journal of Information Display
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• 제7권3호
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• pp.27-30
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• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.3-3
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• 2010

We investigated the influence of the indium content on the threshold voltage ($V_{th}$) shift of sol-gel-derived indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs). Surplus indium composition ratio into IGZO decreases the value of $V_{th}$ of IGZO TFTs showed huge $V_{th}$ shift in the negative direction. $V_{th}$ shift decreases from 10 to -28.2V as Indium composition ratio is increased. Because the free electron density is increased according to variation of the Indium composition ratio.

• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Korean Chemical Engineering Research
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• 제48권6호
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• pp.737-740
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• 2010

높은 누설 전류와 문턱 전압의 이동은 비정질 실리콘(a-Si:H) 트랜지스터(TFT)의 단점이다. 이러한 특성은 게이트 절연체와 활성층 박막의 막 특성, 표면 거칠기와 공정 조건에 따라 영향을 받는다. 본 연구의 목적은 누설 전류와 문턱 전압의 특성을 개선하는데 목적이 있다. 게이트 절연체의 공정 조건에 대해서는 질소를 증가한 증착 공정 조건을 적용하였고, 활성층의 공정 조건에 대해서는 산소를 증가한 공정 조건을 적용하여 전자 포획을 감소시키고 박막의 밀도를 증가시켰다. $I_{off}$는 $65^{\circ}C$ 조건하에서 1.01 pA에서 0.18pA로, ${\Delta}V_{th}$는 -1.89 V에서 -1.22V로 개선되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• 한국고분자학회:학술대회논문집
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• 한국고분자학회 2006년도 IUPAC International Symposium on Advanced Polymers for Emerging Technologies
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• pp.170-170
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• 2006

[ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.