• Electrical & Electronic Materials
• /
• v.9 no.8
• /
• pp.813-818
• /
• 1996

Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$ device shows the memory switching characteristics under d.c. bias. In bulk material, a-As$_{10}$Ge$_{15}$ Te$_{75}$ switching threshold voltage (V$_{th}$) is very high (above 100 volts), but in the case of thin film, V$_{th}$ decreases to a few or ten a few volts. The characteristics of V$_{th}$ depends on the physical dimensions such as the thickness of thin film and the separation between d.c. electrodes, and the annealing conditions. The switching threshold voltage decreases exponentially with increasing annealing temperature and annealing time, but increases linearly with the thickness of thin film and exponentially with increasing the separation between d.c. electrodes. The desirable low switching threshold voltage, therefore, can be obtained by the stabilization through annealing and changing physical dimensions.imensions.sions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.2
• /
• pp.92-97
• /
• 2013

In this paper the author proposes a method of implementing a numerical model for threshold voltage ($V_{th}$) shift in organic thin-film transistors (OTFTs) into SPICE tools. $V_{th}$ shift is first numerically modeled by dividing the shift into sequentially ordered groups. The model is then used to derive a simulations model which takes into simulation parameters and calculation complexity. Finally, the numerical and simulation models are implemented in AIM-SPICE. The SPICE simulation results agree well with the $V_{th}$ shift obtained from an OTFT fabricated without any optimization. The proposed method is also used to implement the stretched-exponential time dependent $V_{th}$ shift in AIM-SPICE and the results show the proposed method is applicable to various types of $V_{th}$ shifts.

• Journal of IKEEE
• /
• v.28 no.1
• /
• pp.110-115
• /
• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.284-292
• /
• 2020

SiC-based devices perform well in high-voltage environments of more than 1200V compared to silicon devices, and are particularly stable at very high temperatures. Therefore, 1700V UMOSFET has been actively researched and developed for the use of electric power systems such as electric vehicles and aircrafts. In this paper, we analysed thermal variations of critical variables (breakdown voltage (BV), on-resistance (R_on), threshold voltage (v_th), and transconductance (g_m)) for the three type 1700V UMOSFETs-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), and Local Floating Superjunction UMOSFET (LFS-UMOSFET). All three devices showed BV increase, R_on increase, v_th decrease, and g_m decrease with increasing temperature. However, there are differences in BV, R_on, v_th, g_m according to the structural differences of the three devices, and the degree and cause of the analysis were compared. All results were simulated using sentaurus TCAD.

• Journal of Information Display
• /
• v.7 no.3
• /
• pp.27-30
• /
• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.3-3
• /
• 2010

We investigated the influence of the indium content on the threshold voltage ($V_{th}$) shift of sol-gel-derived indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs). Surplus indium composition ratio into IGZO decreases the value of $V_{th}$ of IGZO TFTs showed huge $V_{th}$ shift in the negative direction. $V_{th}$ shift decreases from 10 to -28.2V as Indium composition ratio is increased. Because the free electron density is increased according to variation of the Indium composition ratio.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.2
• /
• pp.129-135
• /
• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Korean Chemical Engineering Research
• /
• v.48 no.6
• /
• pp.737-740
• /
• 2010

High leakage current and threshold voltage shift(${\Delta}Vth$) are demerits of a-Si:H TFT. These characteristics are influenced by gate insulator and active layer film quality, surface roughness, and process conditions. The purpose of this investigation is to improve off current($I_{off}$) and ${\Delta}V_{th}$ characteristics. Nitrogen-rich deposition condition was applied to gate insulator, and hydrogen-rich deposition condition was applied to active layer to reduce electron trap site and improve film density. $I_{off}$ improved from 1.01 pA to 0.18 pA at $65^{\circ}C$, and ${\Delta}V_{th}$ improved from -1.89 V to 1.22 V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.76-81
• /
• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• Proceedings of the Polymer Society of Korea Conference
• /
• 2006.10a
• /
• pp.170-170
• /
• 2006

[ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.