• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• ETRI Journal
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• v.37 no.1
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• pp.118-127
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• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06d
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• pp.369-371
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• 2012

Wireless sensor networks have taken immense interest in healthcare systems in recent years. One example of it is in an in vivo sensor that is deployed in critical and sensitive healthcare applications like artificial retina, cardiac pacemaker, drug delivery, blood pressure, internal heat calculation, glucosemonitoring etc. In vivo sensor nodes exhibit temperature that may be very dangerous for human tissues. However, existing in vivo thermal aware routing approaches suffer from hotspot creation, delay, and computational complexity. These limitations motivate us toward an in vivo virtual backbone, a small subset of nodes, connected to all other nodes and involved in routing of all nodes, -based solution. A virtual backbone is lightweight and its fault-tolerant version allows in vivo sensor nodes to disconnect hotspot paths and to use alternative paths. We have formulated the problem as m-connected k-dominating set problem with minimum temperature cost in in vivo sensor network. This is a combinatorial optimization problem and we have been motivated to use evolutionary approach to solve the problem.

• Journal of Korea Multimedia Society
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• v.10 no.6
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• pp.786-798
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• 2007

As we go about our daily lives, people often collect surrounding information and adapt to the situation. Computer development trends show that one wants computers to work like human beings, i.e. computers can sense its context and adapt corresponding to context changes. To implement this expectation, a context aware service layer is needed. In this layer, sensors capture its environment and send this information to the service center. Considering received information as its context, the service center seeks the suitable operation according to the context. Tills paper presents a context aware service which is applied in controlling air-conditioner. The air-conditioner includes sensors which are installed at some special positions in a room. Each of these sensors gathers comfort-influenced information like temperature, humidity and sends them to air-conditioner. The air-conditioner adapts its operation to the environment according to the sensed information. To control the air-conditioner effectively, we use a genetic algorithm which is suitable in adaptation issues. The simulation shows that the room condition can be maintained at a comfortable level by using context-aware services in the operation of the air-conditioning system.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.212-216
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• 2010

Dynamic Thermal Management (DTM) degrades the processor performance for lowering temperature. For this reason, reducing the peak temperature on microprocessors can improve the performance by reducing the performance loss due to DTM. In this study, we analyze various unit selection techniques for computation migration. According to our simulation results, dynamic computation migration based on the thermal difference between the units shows best performance among compared models.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.1-10
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• 2011

Unfortunately, in current microprocessors, increasing the frequency causes increased power consumption and reduced reliability whereas it improves the performance. To overcome the power and thermal problems in the singlecore processors, multicore processors has been widely used. For 2D multicore processors, interconnection is regarded as one of the major constraints in performance and power efficiency. To reduce the performance degradation and the power consumption in 2D multicore processors, 3D integrated design technique has been studied by many researchers. Compared to 2D multicore processors, 3D multicore processors get the benefits of performance improvement and reduced power consumption by reducing the wire length significantly. However, 3D multicore processors have serious thermal problems due to high power density, resulting in reliability degradation. Detailed thermal analysis for multicore processors can be useful in designing thermal-aware processors. In this paper, we analyze the impact of workload distribution, distance to the heat sink, and number of stacked dies on the processor temperature. We also analyze the effects of the temperature on overall system performance. Especially, this paper presents the guideline for thermal-aware multicore processor design by analyzing the thermal problems in 2D multicore processors and 3D multicore processors.