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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs

  • Jang, Cheoljon (Department of Nanoscale Semiconductor Engineering, Hanyang University) ;
  • Chong, Jong-Wha (Department of Electronics Computer Engineering, Hanyang University)
  • Received : 2013.11.21
  • Accepted : 2014.02.03
  • Published : 2014.08.01
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Abstract

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

Keywords

References

  1. K. Banerjee et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on- Chip Integration," Proc. IEEE, vol. 89, no. 5, May 2001, pp. 602-633. https://doi.org/10.1109/5.929647
  2. C.-M. Hung and Y.-L. Lin, "Three-Dimensional Integrated Circuits Implementation of Multiple Applications Emphasizing Manufacture Reuse," Comput. Digit. Techn., IET, vol. 5, no. 3, May 2011, pp. 179-185. https://doi.org/10.1049/iet-cdt.2009.0118
  3. A. Todri et al., "A Study of Tapered 3-D TSVs for Power and Thermal Integrity," IEEE Trans. VLSI, vol. 21, no. 2, Feb. 2013, pp. 306-319. https://doi.org/10.1109/TVLSI.2012.2187081
  4. K. Puttaswamy and G.H. Loh, "Thermal Analysis of a 3D Die- Stacked High-Performance Microprocessor," ACM GLS VLSI, Apr. 2006, pp. 19-24.
  5. A. Jain et al., "Thermal Modeling and Design of 3D Integrated Circuits," ITHERM, Orlando, FL, USA, May 28-31, 2008, pp. 1139-1145.
  6. P. Li et al., "Efficient Full-Chip Thermal Modeling and Analysis," ICCAD, San Jose, CA, USA, Nov. 7-11, 2004, pp. 319-326.
  7. G. Karypis et al., "Multilevel Hypergraph Partitioning: Application in VLSI Domain," IEEE Trans. VLSI, vol. 7, no. 1, Mar. 1999, pp. 69-79. https://doi.org/10.1109/92.748202
  8. G. Karypis and V. Kumar, "Multilevel K-Way Hypergraph Partitioning," ACM/IEEE DAC, June 21-25, 1999, pp. 343-348.
  9. I.H.-R. Jiang and T.-W. Mei, "Generic Integer Linear Programming Formulation for 3D IC Partitioning," SOCC, Belfast, UK, Sept. 9-11, 2009, pp. 321-324.
  10. J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," ICCAD, San Jose, CA, USA, Nov. 7-11, 2004, pp. 306-313.
  11. P. Zhou et al., "3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits," ICCAD, San Jose, CA, USA, Nov. 4-8, 2007, pp. 590-597.
  12. Y. Huang et al., "A Thermal-Driven Force-Directed Floorplanning Algorithm for 3D ICs," CAD/Graphics, Huangshan, China, Aug. 19-21, 2009, pp. 497-502.
  13. P.H. Madden et al., Standard Cell Benchmark Circuits, Binghamton Laboratory for Algorithms, Circuits, and Computer Aided Design. Accessed Nov. 15, 2013. http://vlsicad.cs. inghamton.edu/benchmarks.html