Browse > Article
http://dx.doi.org/10.9708/jksci.2010.15.11.001

Thermal Analysis of 3D Multi-core Processors with Dynamic Frequency Scaling  

Zeng, Min (조선대학교 컴퓨터공학부)
Park, Young-Jin (전남대학교 전자컴퓨터공학부)
Lee, Byeong-Seok (조선대학교 컴퓨터공학부)
Lee, Jeong-A (조선대학교 컴퓨터공학부)
Kim, Cheol-Hong (전남대학교 전자컴퓨터공학부)
Publication Information
Journal of the Korea Society of Computer and Information / v.15, no.11, 2010 , pp. 1-9 More about this Journal
Abstract
As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.
Keywords
Processor Architecture; 3D Multi-core Processor; Thermal Management; Dynamic Frequency Scaling;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 T. Pering, and R. Brodersen, "Energy efficient voltage scheduling for real-time operating systems," in Proceedings of the 4th IEEE Real-Time Technology and Applications Symposium RTAS'98, June. 1998.
2 이병석, 김철홍, 이정아, "부동소수점 응용을 위한 저온 도 마이크로프로세서 설계," 정보과학회 논문지, 제 36권, 제 6호, 532-542쪽, 2009년 9월.   과학기술학회마을
3 C. Sun, L. Shang, and R. P. Dick, "Three-dimentional multicoreprocessor system-on -chip thermal optimization," in Proceedings of the 5th Int. Conf. on Hardware/software codesign and system synthesis, pp. 117-122, Sep, 2007.
4 K. Puttaswamy and G. H. Loh, "Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Perfomance 3D Integraged Processors," in Proceeding of the 13th Int. Symp. on High Performance Computer Architecture," pp. 193-204, Feb, 2007.
5 H. B. Jang, I. Yoon, C. H. Kim, S. Shin, and S. W. Chung, "The Impact of liguid Cooling on 3D Multi-Core Processors," in Proceedings of Int. Conf. on Computer Design, pp. 472-478, Oct, 2009.
6 J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, "A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata," in Proceedings of IEEE international Interconnect Technology Conference, pp.132-134, SanFrancisco, USA, Jun. 2000.
7 SPEC CPU2000 Benchmarks, available at http://www.specbench.org
8 K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature- Aware Micro- architecture: Modeling and Implementation," in Proceedings of the 30th Annual ACM/IEEE international Symposium on Computer Architecture, pp. 83-94, Apr, 2003.
9 D. C. Burger, and T. M. Austin, "The SimpleScalar tool set, version 2.0," ACM SIGARCH CAN, vol. 25, no. 3, pp. 13-25, Jun. 1997.   DOI   ScienceOn
10 D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural- level power analysis and optimizations," in Proceeding s of the 27th International Symposium on Computer Architecture, pp.83-94, Jun. 2000.
11 A. K. Coskun, J. L. Ayala, D. Atienza, T. S. Rosing, and Y. Leblebici, "Dynamic Thermal Management in 3D Multicore Architectures," in Proceedings of Design, Automation & Test in Europe Conference & Exhibition, pp.1410-1415, Nice, France, Apr. 2009.
12 C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, "Three-dimensional chip- multiprocessor run-time thermal management," IEEE Transactions on Computer-Aided Design of Lntegrated Circuits and Systems, vol.27, no.8, pp.1479-1492, Aug. 2008.   DOI   ScienceOn
13 K. Puttaswamy, and G. H. Loh, "Thermal Analysis of a 3D Die Stacked High Performance Microprocessor," in Proceedings of ACM GreatLakes Symposium on VLSI, pp.19-24, Philadephia, USA, May. 2006.
14 D. H. Kim, K. Athikulwongse, S. K. Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout," in Proceedings of the 2009 International Conference on Computer-Aided Design, pp.674-680, California, USA, Nov. 2009.
15 D. Brooks and M. Martonosi, "Dynamic thermal management for high-performance microprocessors," in Proceedings of the 27th International Symposium on Computer Architecture, pp.83-94, Jan. 2001.
16 B. Black, M. M. Annavaram, E. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. P. Shen, and C. Webb, "Die stacking (3D) microarchitecture," in Proceedings of the 39th International Symposiumon Microarchitecture, pp.469-479, Orlando, USA, Dec. 2006.
17 J. Cong, G. J. Luo, J. Wei, and Y. Zhang, "Thermal -Aware 3D IC Placement Via Transformation," in Proceedings of ASP-DAC, pp.780-785, Yokohama, Japan, Jan. 2007.
18 K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron, "A case for thermal-aware floor planning at the microarchitectural level," Journal of Instruction-Level Parallelism, vol.7, pp.1-16, 2005.