• Journal of Power Electronics
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• v.9 no.5
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• pp.757-771
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• 2009

This paper proposes a systematic approach to the modeling of the small-signal characteristics of three-phase bridge boost rectifiers under non-sinusoidal conditions. The main obstacle to the conventional synchronous d-q frame modeling approach is that it is unable to identify a steady-state under non-sinusoidal conditions. However, for most applications under non-sinusoidal conditions, the current loops of boost rectifiers are designed to have a bandwidth that is much higher than typical harmonics frequencies in order to achieve good current control for these harmonic components. Therefore a quasi-static method is applied to the proposed modeling approach. The converter small-signal characteristics developed from conventional synchronous frame modeling under different operating points are investigated and a worst case point is then located for the current loop design. Both qualitative and quantitative analyses are presented. It is observed that operating points influence the converter low frequency characteristics but hardly affect the dominant poles. The relationship between power stage parameters, system poles and zeroes is also presented which offers good support for the system design. Both the simulation and experimental results verified the analysis and proposed modeling approach. Finally, the practical case of a parallel active power filter is studied to present the modeling approach and the resultant regulator design procedure. The system performance further verifies the whole analysis.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.201-208
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• 2015

The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.9
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• pp.1315-1322
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• 2015

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• Journal of Power Electronics
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• v.18 no.3
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• pp.863-870
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• 2018

The traditional power control theories for the harmonic reduction methods in multilevel inverters are found to be unreliable under unbalanced load conditions. The unreliability in harmonic mitigation is caused by voltage fluctuations, non-linear loads, the use of power switches, etc. In general, the harmonics are reduced by filters. However, such devices are an expensive way to provide a smooth and fast response to secure power systems during dynamic conditions. Hence, the Decoupled Double Synchronous Reference Frame (DDSRF) theory combined with a State Delay Controller (SDC) is proposed to achieve a harmonic reduction in power systems. The DDSRF produces a sinusoidal harmonic that is the opposite of the load harmonic. Then, it injects this harmonic into power systems, which reduces the effect of harmonics. The SDC is used to reduce the delay between the compensation time for power injection and the generation of a reference signal. The proposed technique has been simulated using MATLAB and its reliability has been verified experimentally under unbalanced conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1176-1189
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• 2016

In this paper, a novel quasi-direct power control (Q-DPC) scheme based on a resonant frequency adaptive proportional-resonant (PR) current controller with a variable frequency resonant phase locked loop (RPLL) is proposed, which can achieve a fast power response with a unity power factor. It can also adapt to variations of the generator frequency in T-type Three-level shaft synchronous generator (SSG) converters. The PR controller under the static α-β frame is designed to track ac signals and to avert the strong cross coupling under the rotating d-q frame. The fundamental frequency can be precisely acquired by a RPLL from the generator terminal voltage which is distorted by harmonics. Thus, the resonant frequency of the PR controller can be confirmed exactly with optimized performance. Based on an instantaneous power balance, the load power feed-forward is added to the power command to improve the anti-disturbance performance of the dc-link. Simulations based on MATLAB/Simulink and experimental results obtained from a 75kW prototype validate the correctness and effectiveness of the proposed control scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.356-362
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• 2015

This paper presents a current control strategy in the synchronous reference frame for a single-phase PWM converter, which ensures sinusoidal input current control under the distorted source voltage and frequency condition. Given that the distorted source voltage distorts the phase angle for PWM converter control, the input current contains the same harmonics as the source voltage. Aside from the distorted voltage, the variation in source frequency reduces the performance of input current control. To achieve sinusoidal input current control under the distorted source voltage and frequency condition, this paper proposes a compensation strategy of current reference with the distortion component extracted from the phase angle and a detection strategy of frequency variation from the output of a synchronous reference frame phase-lock loop. The experimental results confirm the validity of the proposed method under the distorted source voltage and frequency condition.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.8
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• pp.405-412
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• 2003

This paper presents a three-phase Line-Interactive uninterruptible power supply (UPS) system with series-parallel active power-line conditioning capabilities, using synchronous reference frame (SRF) based controller, which allows an effective power factor correction, source harmonic voltage compensation, load harmonic current suppression, and output voltage regulation. The three-phase UPS system consists of two active power compensator topologies. One is a series active compensator, which works as a voltage source in phase with the source voltage to have the sinusoidal source current and high power factor under the deviation and distortion of the source voltage. The other is a parallel active compensator which works as a conventional sinusoidal voltage source in phase with the source voltage, providing to the load a regulated and sinusoidal voltage with low THD (total harmonic distortion). The control algorithm using SRF method and the active power flow through the Line-interactive UPS systems are described and studied. The simulation and experimental results are depicted in this paper to show the effect of the proposed algorithm.