• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Journal of Power Electronics
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• v.15 no.1
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• pp.131-145
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• 2015

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

• ETRI Journal
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• v.41 no.4
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• pp.536-548
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• 2019

In this study, an electronically steerable parasitic array radiator (ESPAR) antenna via analog radio frequency (RF) switches for a single RF chain MIMO system is presented. The proposed antenna elements are spaced at ${\lambda}/64$, and the antenna size is miniaturized via a dielectric radome. The optimum reactance load value is calculated via the beamforming load search algorithm. A switch simplifies the design and implementation of the reactance loads and does not require additional complex antenna matching circuits. The measured impedance bandwidth of the proposed ESPAR antenna is 1,500 MHz (1.75 GHz-3.25 GHz). The proposed antenna exhibits a beam pattern that is reconfigurable at 2.48 GHz due to changes in the reactance value, and the measured peak antenna gain is 4.8 dBi. The reception performance is measured by using a $4{\times}4$ BPSK signal. The measured average SNR is 17 dB when using the proposed ESPAR antenna as a transmitter, and the average SNR is 16.7 dB when using a four-conventional monopole antenna.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.172-177
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• 2014

We present on a threshold switching device based on AsGeTeSi material which is significantly improved by two $N_2$ processes: reactive $N_2$ during deposition, and $N_2$ plasma hardening. The introduction of N2 in the two-step processing enables a stackable and thermally stable device structure, is allowing integration of switch and memory devices for application in nano scale array circuits. Despite of its good threshold switching characteristics, AsTeGeSi-based switches have had key issues with reliability at a high temperature to apply resistive memory. This is usually due to a change in a Te concentration. However, our chalconitride switches(AsTeGeSiN) show high temperature stability as well as high current density over $1.1{\times}10^7A/cm^2$ at $30{\times}30(nm^2)$ celll. A cycling performance of the switch was over $10^8$ times. In addition, we demonstrated a memory cell consisted of 1 switch-1 resistor (1S-1R) stack structure using a TaOx resistance memory with the AsTeGeSiN select device.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.81-89
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• 2007

This paper presents a parallel distributed implementation of the GHT (generalized Hough transform) for the fast processing on the MPI-based PC cluster. We tried to achieve the higher speedup mainly by alleviating the communication overhead through the pipelined broadcast and accumulator array partition strategy and by time overlapping of the communication and the computation over entire process. Experimental results show that nearly linear speedup is reachable by the proposed method on the MPI-based PC clusters connected through 100Mbps Ethernet switch.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.4 s.247
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• pp.306-313
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• 2006

Automated material handling system is being used as a method to reduce manufacturing cost in the semiconductor and flat panel displays (FPDs) manufacturing process. Those are considering switch-over from the traditional cassette system to single-substrate transfer system to reduce raw materials of stocks in the processing line. In the present study, the wafer transportation speed has been evaluated by numerical and experimental method for three propulsion nozzle array (face, front, rear) in an air levitation system. Test facility for 300 mm wafer was equipped with two control tracks and a transfer track of 1,500mm length. The diameter of propulsion nozzle is 0.8mm and air velocity of wafer propulsion is $50\sim150m/s$. We found that the experimental results of the wafer transportation speed were well agreed with the numerical ones. Namely, the predicted values of the maximum wafer transportation speed are higher than those values of experimental data by 16% and the numerical result of the mean wafer transportation speed is higher than the experimental result within 20%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.308-315
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• 2002

In this paper, the 5-bit digital phase shiftier with 10 InGaAs HEMTs is designed and fabricated for U.S. mobile DBS receiving active phased array antenna system in 12 GHz band. 11.25 $^{\circ}$, 22.5$^{\circ}$ and 45$^{\circ}$ phase bits are designed in leaded-line type. 90$^{\circ}$ and 180$^{\circ}$ phase bits are designed in reflection type combined with ring hybrid. The return loss more than 17.5 ㏈, insertion louts less than 7.8 ㏈, and maximum phase error of $\pm$6$^{\circ}$for 32 phase responses are measured in 12.2 GHz~ 12.7 GHz band.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

• Convergence Security Journal
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• v.17 no.2
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• pp.41-51
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• 2017

The explosive increase in the range of Internet usage gradually makes the speed and capacity of network high-speed, rapidly evolving it into mass storage. Accordingly, network equipment such as switch and router are coping with it through hardware-based rapid technological evolution, but as the technological development of the most basic and essential network security system in the hyper-connected society requires frequent alterations and updates about the security issues and signatures of tens of thousands, so it is not easy to overcome the technical limitations based on the software. In this paper, to improve problems in installing and operating such anti-DDoS devices, we propose a Hi-DPI algorithm best reflecting the hardware characteristics and parallel processing characteristics of FPGA (Field Programmable Gate Array), and would verify the practicality.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.61-64
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• 2017

A phase shifter is one of the key components that change the phase of an individual antenna in millimeter-wave phased array system. This paper presents a low-loss phase shifter design with two parallel 2-state amplifiers. To get the same gain of $0^{\circ}/180^{\circ}$ each state, delay lines are in the middle of each stage of the 2-Stage amplifiers. Normally, when adding AMPs in parallel, a power combiner/divider such as Wilkinson Power Combiner/Divider is added, but they are directly connected because it can cause added losses in silicon wafer. The measured data shows 12dB gain and 174-degree phase difference at 5GHz.