• 한국초전도ㆍ저온공학회논문지
• /
• 제15권2호
• /
• pp.29-33
• /
• 2013

The understanding of the strain dependence of critical current, $I_c$, in the reversible region is important for the evaluation of the performance of coated conductor (CC) tapes in practical applications. In this study, the stress/strain tolerance of $I_c$ in GdBCO CC tapes with stainless steel substrate stabilized by additional Cu and brass laminate was analyzed quantitatively through $I_c$-strain measurement at 77 K under self-field. The variation in irreversible strain limits of CC tapes by the addition of stabilizing layers was analyzed through the consideration of the pre-strain induced on the GdBCO coating film. The results were then compared with the ones previously reported for GdBCO CC tapes with Hastelloy substrate. As a result, GdBCO CC tapes with stainless steel substrate showed much higher strain tolerance of $I_c$ as compared with those adopting Hastelloy substrate.

• 마이크로전자및패키징학회지
• /
• 제23권3호
• /
• pp.63-67
• /
• 2016

본 논문에서는 폴리머 기반의 유연 기판 위 적층 된 다양한 필름의 굽힘 탄성계수의 간접 측정법을 소개한다. 패키징 기판의 다양한 적층 재료들의 탄성계수는 기계적으로 신뢰성 있는 전자기기 개발에 결정적이지만, 기판과 매우 견고히 접합하고 있는 적층 필름을 온전히 떼어 내어 자유지지형(free-standing) 시편을 만들기 어렵기 때문에 그 측정이 쉽지 않다. 이를 해결하기 위해 본 연구에서는 필름-기판의 복합체 시편에 대한 3점 굽힘을 진행하였고 시편 단면에 면적 변환법(area transformation rule)을 적용한 응력 해석을 수행하였다. 탄성계수를 알고 있는 기판에 대하여, 굽힘 시험으로 얻은 다층 시편의 강성으로부터 필름과 기판의 탄성계수 비를 계산하였으며, 전기 도금 구리 시편을 이용하여 양면 적층, 단면 적층의 두 가지 해석 모델이 실험 평가되었다. 또한 주요 절연체 적층 재료인 prepreg (PPG)와 dry film solder resist (DF SR)의 굽힘 탄성계수가 양면 적층 시편 형태로 측정 되었다. 결과로써 구리 110.3 GPa, PPG 22.3 GPa, DF SR 5.0 GPa이 낮은 측정 편차로 측정 됨으로써 본 측정법의 정밀도와 범용성을 검증하였다.

• 대한금속재료학회지
• /
• 제47권5호
• /
• pp.322-329
• /
• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 디스플레이 광소자 분야
• /
• pp.65-68
• /
• 2002

The effect of low-temperature ZnO buffer layer has been investigated for the optical properties of ZnO thin films. ZnO buffers and thin films have been deposited using the pulsed laser deposition technique. ZnO buffer layers were grown at $200^{\circ}C$ with various thickness of 0 to 60 nm, followed by raising the substrate temperature to $400^{\circ}C$ to grow $2{\mu}m$ ZnO thin films. The buffer layers could relax stresses induced by the lattice mismatch and different thermal expansion coefficients between ZnO thin films and sapphire substrate. In order to identify the optical properties of ZnO thin films, PL measurement was used. From the results of PL measurement, all the fabricated ZnO thin films with buffer layers have shown intensive UV emission with a narrow linewidth. ZnO thin films with buffer layer of 20 nm have shown the strongest UV emission. It was found that the use of ZnO buffer layer plays an important role to improve the intensive UV emission of the ZnO thin films.

• 대한기계학회논문집A
• /
• 제32권9호
• /
• pp.720-727
• /
• 2008

Microfluidic single chip integrating thermopneumatic micropump and micro check valve are developed. The micropump and micorvalve are made of biocompatible materials, glass and PDMS, so as to be applicable to the biochip. By using the passive-type check valve, backward flow and fluid leakage are blocked and flow control is stable and precise. The chip is composed of three PDMS layers and a glass substrate. In the chip, flow channel and pump chamber were made on the PDMS layers by the replica molding technique and pump heater was made on the glass substrate by Cr/Au deposition. Diameter of the pump chamber is 7 mm and the width and depth of the channel are 200 and $180{\mu}m$, respectively. The PDMS layers chip and the heater deposited glass chip are combined by a jig and a clamp for pumping operation, and they are separable so that PDMS chip is used as a disposable but the heater chip is able to be used repeatedly. Pumping performance was simulated by CFD software and investigated experimentally. The performance was the best when the duty ratio of the applied voltage to the heater was 33%.

• 전자공학회논문지A
• /
• 제32A권3호
• /
• pp.89-99
• /
• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.452-455
• /
• 2003

[ $ZrO_2$ ] dielectric layers were grown on the p-type Si (100) substrate by metalorganic molecular beam epitaxy(MOMBE). Zrconium t-butoxide, $Zr(O{\cdot}t-C_4H_9)_4$ was used as a Zr precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and the properties of the $ZrO_2$ layers were evaluated by X-ray diffraction, high frequency capacitance-voltage measurement. and HF C-V measurements have shown that $ZrO_2$ layer grown by MOMBE has a high dielectric constant (k=18-19). The growth rate is affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
• /
• pp.873-875
• /
• 1999

We have fabricated good quality superconducting $YBa_{2}Cu_{3}O_{7-\delta}$ thin films on Hastelloy(Ni-Cr-Mo alloys) metallic substrate with $CeO_2$ and $BaTiO_3$ buffer layers in-situ by pulsed laser deposition in a multi-target processing chamber. We have chosen $CeO_2$ as a buffer layer which has cubic structure of $5.41{\AA}$ lattice parameter and only 0.2% of lattice mismatch with YBCO. $CeO_2$ layer may be helpful for power transmission due to its conducting property. In order to enhance the crystallization of YBCO films on metallic substrates. we deposited $CeO_2$ and $BaTiO_3$ buffer layers at various temperatures. The YBCO superconducting tape fabricated with $BaTiO_3$ and $CeO_2$ buffer layers shows 85K of transition temperature and about $8.4{\times}10^4A/cm^2$ of critical current density at 77K.

• 한국표면공학회지
• /
• 제43권4호
• /
• pp.170-175
• /
• 2010

The GaAs epitaxial layers were grown on Si(100) substrates by molecular beam epitaxy(MBE) using the two-step method. The Si(100) substrates were cleaned with different surface cleaning method of vacuum heating, As-beam, and Ga-beam at the substrate temperature of $800^{\circ}C$. Growth temperature and thickness of the GaAs epitaxial layer were $800^{\circ}C$ and 1 ${\mu}m$, respectively. The surface structure and epitaxial growth were observed by reflection high-energy electron diffraction(RHEED) and scanning electron microscope(SEM). Just surface structure of the Si(100) substrate cleaned by Ga-beam at $800^{\circ}C$ shows double domain ($2{\times}1$). RHEED patterns of the GaAs epitaxial layers grown on Si(100) substrates with cleaning method of vacuum heating, As-beam, and Ga-beam show spot-like, ($2{\times}4$) with spot, and clear ($2{\times}4$). From SEM, it is found that the GaAs epitaxial layers grown on Si(100) substrates with Ga-beam cleaning has a high quality.

• 한국광학회지
• /
• 제26권2호
• /
• pp.115-120
• /
• 2015

광축의 각도가 서로 다른 두 단축이방성 박막이 다층박막 기층시료 위에 코팅되어 있을 때 비스듬히 입사한 빛의 유효반사계수 표현들을 유도하였다. 유효반사계수로부터 타원상수 표현들을 구하고 이 타원상수의 단축이방성 박막 광축각도 의존성으로부터 단축이방성 박막의 표면 이방성에 의한 효과와 주층 이방성에 의한 효과를 구분하여 해석할 수 있도록 하였다.