• Macromolecular Research
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• v.12 no.1
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• pp.53-62
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• 2004

We have prepared polymer composites of low-density polyethylene (LDPE) and ionomers (Surlyn 8940) containing polar segments and metal ions by melt blending with carbon black (CB) as a conductive filler. The resistivity and positive temperature coefficient (PTC) of the ionomer/LDPE/CB composites were investigated with respect to the CB content. The ionomer content has an effect on the resistivity and percolation threshold of the polymer composites; the percolation curve exhibits a plateau at low CB content. The PTC intensity of the crosslinked ionomer/LDPE/CB composite decreased slightly at low ionomer content, and increased significantly above a critical concentration of the ionomer. Irradiation-induced crosslinking could increase the PTC intensity and decrease the NTC effect of the polymer composites. The minimum switching current (Ι$\sub$trip/) of the polymer composites decreased with temperature; the ratio of Ι$\sub$trip/ for the ionomer/LDPE/CB composite decreased to a greater extent than that of the LDPE/CB composite. The average temperature coefficient of resistance (${\alpha}$$\sub$T/) for the polymer composites increased in the low-temperature region.

• Journal of the Korean Society of Safety
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• v.5 no.1
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• pp.19-29
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• 1990

The objective of this paper is to investigate the effect of residual stresses on the $\Delta$K$\sub$th/ and fatigue crack growth behavior of butt weldments. For this purpose, transverse butt sutmerged arc welding was performed on SM50A steel plate and CT(compact tension) specimens which loading direction is perpendicular to weld bead were selected. Welding residual stresses distribution on the specimen was determined by hole drilling method. The case of crack located parallel to weld bead, the states of as weld and PWHT, $\Delta$K$\sub$th/ of specimens(HAZ, weld zone) was higher than that of the base metal probably because of the compressive residual stresses of crack tip. In low $\Delta$K region, it is estimated that the effects of residual stresses for da/dN are great. In region II, the da/dN of weldments in as weld state was lower than that of the base metal. Though da/dN of Weldments in PWHT state was similar to that of the base metal. The constant of power law, m in two states consisted with the base metal. Therefore , it is estimated that the value of m is not affected by residual stresses. Fatigue crack growth behavior of weldments consisted with the base metal considering the effective stress intensity factor range($\Delta$K$\sub$eff/) included the effect of initial residual stress(Kres). Thus, we can predict the fatigue crack growth behavior of weldment by knowing the distribution of initial residual stress at the crack tip.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.5
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• pp.55-63
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• 2011

This paper describes new moving target detection technique combining two algorithms to detect targets and reject clutters in video frame images for surveillance system: One obtains the region of moving target using phase correlation method using $N{\times}M$ sub-block images in frequency domain. The other uses adaptive threshold using learning weight for extracting target candidates in subtracted image. The block region with moving target can be obtained using the characteristics that the highest value of phase correlation depends on the movement of largest image in block. This technique can be used in camera motion environment calculating and compensating camera movement using FFT phase correlation between input video frame images. The experimental results show that the proposed algorithm accurately detects target(s) with a low false alarm rate in variety environment using the receiver operating characteristics (ROC) curve.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.1-8
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• 2013

This paper presents a variable gain amplifier(VGA) without passive devices. This VGA employes the architecture of current feedback amplifier and variable gain can be achieved by using the GM ratios of two trans-conductance(gm) circuits. To obtain linearity and high gain, it uses current division technique and source degeneration in feedback GM circuits. Input trans-conductance(GM) circuit was biased by using a tunable voltage controller to obtain variable gain. The prototype of the VGA is designed in $0.35{\mu}m$ CMOS technology and it is operating in sub-threshold region for low power consumption. The the gain of proposed VGA is varied from 23dB to 43dB, and current consumption is $2.82{\mu}A{\sim}3{\mu}A$ at 3.3V. The area of VGA is 1$120{\mu}m{\times}100{\mu}m$.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.7-11
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• 2006

The changes of the electrical conductivity in chalcogenide amorphous semiconductors, $Ge_{1}Se_{1}Te_{2}$, have been studied. A phase change random access memory (PRAM) device without an access transistor is successfully fabricated with the $Ge_{1}Se_{1}Te_{2}$-phase-change resistor, which has much higher electrical resistivity than $Ge_{2}Sb_{2}Te_{5}$ and its electric resistivity can be varied by the factor of $10^5$ times, relating with the degree of crystallization. 100 nm thick $Ge_{1}Se_{1}Te_{2}$ thin film was formed by vacuum deposition at $1.5{\times}10^{-5}$ Torr. The static mode switching (DC test) is tested for the $100\;{\mu}m-sized$ $Ge_{1}Se_{1}Te_{2}$ PRAM device. In the first sweep, the amorphous $Ge_{1}Se_{1}Te_{2}$ thin film showed a high resistance state at low voltage region. However, when it reached to the threshold voltage, $V_{th}$, the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The pulsed mode switching of the $20{\mu}m-sized$ $Ge_{1}Se_{1}Te_{2}$ PRAM device showed that the reset of device was done with a 80 ns-8.6 V pulse and the set of device was done with a 200 ns-4.3 V pulse.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.63-71
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• 2009

In this study, we propose a revised dynamic ROI (Region-of-Interest) coding method in which the focused ROI is automatically extracted without help from users during the recovery process of low DOF (Depth-of-Field) JPEG2000 image. The proposed method creates edge mask information using high frequency sub-band data on a specific level in DWT (Discrete Wavelet Transform), and then identifies the edge code block for a high-speed ROI extraction. The algorithm scans the edge mask data in four directions by the unit of code block and identifies the edge code block simply and fastly using a edge threshold. As the results of experimentation applying for Implicit method, the proposed method showed the superiority in the side of speed and quality comparing to the existing methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.9-15
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• 2004

We present a new unified analytical front surface potential model, which can accurately describe the transitions between the partially-depleted (PD) and the fully-depleted (FD) regimes with an analytical expression for the critical voltage V$_{c}$ delineating the PD and the FD region. It is valid in all regions of operation (from the sub -threshold to the strong inversion) and has the shorter calculation time than the iterative procedure approach. A charge sheet model based on the above explicit surface potential formulation is used to derive a single formula for the drain current valid in all regions of operation. Most of the secondary effects can be easily included in the charge sheet model and the model accurately reproduces various numerical and experimental results. No discontinuity in the derivative of the surface potential is found even though three types of smoothing functions are used. More importantly, the newly introduced parameters used in the smoothing functions do not strongly depend on the process parameter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.