• 제목/요약/키워드: sub-threshold

검색결과 434건 처리시간 0.037초

파라메트릭 배열을 이용한 해저지층 탐사 알고리즘 (Sub-bottom Profiling Algorithm using Parametric Array)

  • 이종현;이재일;배진호
    • 한국해양공학회지
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    • 제28권1호
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    • pp.55-63
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    • 2014
  • In this paper, we propose an threshold-based Schur algorithm for estimating the media characteristics of sub-bottom multi-layers by using the signal generated by a parametric array transducer. We use the KZK model to generate a parametric array signal, and use the proposed threshold-based Schur algorithm for estimating the reflection coefficients of multiple sea bottom layers. Using computer simulation, we verify that the difference frequency component generated by the KZK model prevails over the signals of primary frequencies at long range. For the simulation, we use the transmit signal generated by the KZK and the reflected signal obtained from a lattice filter model for the seawater and sub-bottom of multi-level non-homogeneous layers. Through the simulation, we verify that the proposed threshold-based Schur algorithm can give much more accurate and efficient estimates of the reflection coefficients than methods using received signal, matched filter output signal, and normal Schur algorithm output.

Strain-dependent-deformation property of Gyeongju compacted bentonite buffer material for engineered barrier system

  • Ivan Jeff Navea;Jebie Balagosa;Seok Yoon;Yun Wook Choo
    • Nuclear Engineering and Technology
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    • 제56권5호
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    • pp.1854-1862
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    • 2024
  • This study aims to investigate the strain-dependent-deformation property of Gyeongju bentonite buffer material. A series of unconfined compressive tests were performed with cylindrical specimens prepared at varying dry densities (𝜌d = 1.58 g/cm3 to 1.74 g/cm3) using cold isostatic pressing technique. It is found that as 𝜌d increase, the unconfined compressive strength (qu), failure strain, and elastic modulus (E) of Gyeongju compacted bentonite (GCB) increases. Normalized elastic modulus (Esec/Emax) degradation curves of GCB specimens are fitted using Ramberg-Osgood model and the elastic threshold strain (𝜀e,th) is determined through the fitted curves. The strain-dependency of E and Poisson's ratio (v) of GCB were observed. E and v were measured constant below 𝜀e,th of 0.14 %. Then, E decreases while v increases after exceeding the strain threshold. The Esec/Emax degradation curves of GCB in this study suggests wider linear range and higher linearity than those of sedimentary clay in previous study. On top of that, the influence of 𝜌d is observed on Esec/Emax degradation curves of GCB, showing a slight increase in 𝜀e,th with increase in 𝜌d. Furthermore, an empirical model of qu with 𝜌d and a correlation model between qu and E are proposed for Gyeongju bentonite buffer materials.

무반사 면을 갖는 DFB 레이저의 빔 분포 시뮬레이션과 검정 (Simulation and Examination for Beam Profile of DFB Laser with an Anti-reflection Coated Mirror)

  • 권기영;기장근
    • 한국소프트웨어감정평가학회 논문지
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    • 제16권1호
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    • pp.55-63
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    • 2020
  • 광대역 광통신 시스템에 사용되는 레이저는 우수한 주파수 선택성과 모드 안정성을 가져야한다. DFB(Distributed Feedback) 레이저는 고주파로 전류 변조를 하더라도 발진 주파수의 변화가 적다. 본 연구에서는 1.55um의 파장을 갖는 DFB 레이저에서 굴절률 격자와 이득 격자가 동시에 존재할 때, 오른쪽 거울 면에 반사가 일어나지 않도록 유전막 코팅을 하여 ρr=0 이 되도록 하였다. 문턱에서 최소 이득을 필요로 하는 제 1모드에 대하여, 종 방향으로의 발진 모드의 빔 분포와 방사전력비 Pl/Pr를 ρl의 위상=π인 경우와 ρl의 위상=π/2인 경우에 대하여 비교 검증했다. ρl의 위상=π인 경우, 낮은 문턱 전류와 높은 주파수 안정성을 얻기 위해서는, κL이 8보다 커야 한다. ρl의 위상=π/2인 경우, 낮은 문턱 전류를 위해서는 κL=1.0이 되도록 해야 하고, 이때 발진 주파수는 격자 주파수와 일치한다. 반사 방지 코팅을 하지 않은, 두 개의 거울 면을 가진 1.55um의 파장을 갖는 DFB 레이저보다, 한쪽 거울 면에 무반사 코팅을 한 경우에 모드 선별성이 훨씬 크다.

MgxZn1-xO를 활용한 Multi-layer 구조 LED 특성에 관한 연구 (The Characteristics of Multi-layer Structure LED with MgxZn1-xO Thin Films)

  • 손지훈;김상현;장낙원;김홍승
    • 한국전기전자재료학회논문지
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    • 제25권10호
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    • pp.811-816
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    • 2012
  • The effect of co-sputtering condition on the structural properties of $Mg_xZn_{1-x}O$ thin films grown by RF magnetron co-sputtering system was investigated for manufacturing ZnO/MgZnO structure LED. $Mg_xZn_{1-x}O$ thin films were grown with ZnO and MgO target varying RF power. Structural properties were investigated by X-ray diffraction (XRD) and Energy dispersive spectroscopy (EDS). The ZnO thin films have sufficient crystallinity on the high RF power. As RF power of ZnO target increased, the contents of MgO in the $Mg_xZn_{1-x}O$ film decreased. LED was manufactured using ZnO/MgZnO multi-layer on p-GaN/$Al_2O_3$ substrate. Threshold voltage of multi-layer LED was appeared at 8 V, and it was luminesced at wave length of 550 nm.

Tapering과 Ferroelectric Polarization에 의한 3D NAND Flash Memory의 Lateral Charge Migration 분석 (The Analysis of Lateral Charge Migration at 3D-NAND Flash Memory by Tapering and Ferroelectric Polarization)

  • 이재우;이종원;강명곤
    • 전기전자학회논문지
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    • 제25권4호
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    • pp.770-773
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    • 2021
  • 본 논문에서는 tapering과 ferroelectric(HfO2)구조가 적용된 3D NAND flash memory의 프로그램 이후 시간경과에 따른 retention특징을 분석했다. Nitride에 trap된 전자는 시간이 지남에 따라 lateral charge migration이 발생한다. 프로그램 이후 시간이 지남에 따라 trap된 전자가 tapering에 의해 두꺼워진 채널 쪽으로 lateral charge migration이 더 많이 발생하는 것을 확인했다. 또한 Oxide-Nitride-Ferroelectric (ONF) 구조는 polarization에 의해 lateral charge migration이 완화되기 때문에 기존 Oxide-Nitride-Oxide (ONO) 구조 보다 문턱전압(Vth)의 변화량이 줄어든다.

평면구조 P-MOS DRAM 셀의 커패시터 VT 이온주입의 최적화 (Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell)

  • 장성근;김윤장
    • 한국전기전자재료학회논문지
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    • 제19권2호
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    • pp.126-129
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    • 2006
  • We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

A Low-Power Register File with Dual-Vt Dynamic Bit-Lines driven by CMOS Bootstrapped Circuit

  • Lee, Hyoung-Wook;Lee, Hyun-Joong;Woo, Jong-Kwan;Shin, Woo-Yeol;Kim, Su-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권3호
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    • pp.148-152
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    • 2009
  • Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

The Pulsed Id-Vg methodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

  • Young, Chadwin D.;Heh, Dawei;Choi, Ri-No;Lee, Byoung-Hun;Bersuker, Gennadi
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권2호
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    • pp.79-99
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    • 2010
  • Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method

  • Kihoon Nam;Chanyang Park;Jun-Sik Yoon;Hyeok Yun;Hyundong Jang;Kyeongrae Cho;Ho-Jung Kang;Min-Sang Park;Jaesung Sim;Hyun-Chul Choi;Rock-Hyun Baek
    • Nanomaterials
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    • 제12권11호
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    • pp.1808-1817
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    • 2022
  • A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the Vth window between the erase and program Vth. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the Vth window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (NTD and NTA) and their standard deviations (σTD and σTA) were found to most strongly impact the Vth window. As they increased, the Vth window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the Vth window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구 (A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure)

  • 엄금용;오환술
    • 한국전기전자재료학회논문지
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    • 제13권9호
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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