• Title/Summary/Keyword: sub channel

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A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure (STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.9
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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A Study on the Validity of C-V Method for Extracting the Effective Channel Length of MOSFET) (MOSFET의 Effective Channel Length를 추출하기 위한 C-V 방법의 타당성 연구)

  • 이성원;이승준;신형순
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.10
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    • pp.1-8
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    • 2002
  • C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

Extracting the Effective Channel Length of MOSFET by Capacitance - Voltage Method. (Capacitance - Voltage 방법을 이용한 MOSFET의 유효 채널 길이 추출)

  • 김용구;지희환;박성형;이희덕
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.679-682
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    • 2003
  • Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

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A Study on the Channel-Width Dependent Hot-Carrier Degradation of nMOSFET with STI (STI구조를 갖는 nMOSFET의 채널 너비에 따른 Hot-Carrier 열화 현상에 관한 연구)

  • 이성원;신형순
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.638-643
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    • 2003
  • Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

Numerical Study on Performance of PEMFC with Block and Sub-channel of Cathode Flow Field (캐소드 유로에서 블록과 서브 채널의 고분자전해질 연료전지의 성능에 관한 전산해석 연구)

  • Jo, Seonghun;Kim, Junbom
    • Applied Chemistry for Engineering
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    • v.32 no.6
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    • pp.613-620
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    • 2021
  • A flow channel shape of PEMFC has an influence on the internal flow uniformity. If the reactant distribution in a flow path is not uniform during operation, both catalyst deactivation and mechanical damage of membrane could occur resulting in decreasing the membrane electrode assembly (MEA) durability. Numerous studies concerning flow design have been conducted to make smooth supply and uniform distribution of reactants in fuel cells. The baffle of flow path could improve fuel cell performance through the forced convection effect. A sub-channel, as an additional air flow path, could increase the reactant concentration and reduce the mass transfer loss via a smooth water discharge. In this study, computational fluid dynamics (CFD) was used to analyze the effect of blocks and sub-channels on the current density and oxygen concentration of the fuel cell. As a result, the limit current density and oxygen concentration at a rear block increased when using blocks and sub-channels in a flow channel. In particular, the current density increased significantly when the sub-channel was placed between two blocks. Also, the sub-channel position was optimized by analyzing the oxygen concentration, and the oxygen concentration was recovered at a rear block in the fuel cell.

A Triple-Probe Channel NO2S2-Macrocycle: Synthesis, Sensing Characteristics and Crystal Structure of Mercury(II) Nitrate Complex

  • Lee, Ji-Eun;Choi, Kyu-Seong;Seo, Moo-Lyong;Lee, Shim-Sung
    • Bulletin of the Korean Chemical Society
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    • v.31 no.7
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    • pp.2031-2035
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    • 2010
  • A triple-probe channel type chemosensor based on an $NO_2S_2$-macrocycle functionalized with phenyltricyanovinyl group was synthesized and its sensing characteristics were examined. The pink-red solution of L changed selectively to pale yellow upon addition of $Hg^{2+}$. The selective fluorometric response of L to all the tested metal ions was studied. The results showed that a large enhancement of the fluorescence of L was observed only in the case of $Hg^{2+}$. In addition, L showed large anodic shift (~ 0.3 V) for the addition of excess $Hg^{2+}$. Through above three observed results by the different techniques, we confirmed that the proposed chemosensor acts as the multiple-probe channel sensing material. The crystal structure of mercury(II) nitrate complexs of L which shows a 1-D polymer network with a formula $[Hg_2(L)_2(NO_3)_2({\mu}-NO_3)_2]_n$ was also reported.

The Change of I-V Characteristics by Gate Voltage Stress on Few Atomic Layered MoS2 Field Effect Transistors (수 원자층 두께의 MoS2 채널을 가진 전계효과 트랜지스터의 게이트 전압 스트레스에 의한 I-V 특성 변화)

  • Lee, Hyung Gyoo;Lee, Gisung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.3
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    • pp.135-140
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    • 2018
  • Atomically thin $MoS_2$ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, $MoS_2$ single-crystal as a transistor channel after transfer onto a $SiO_2/Si$ substrate. The $MoS_2$ FETs displayed n-channel characteristics with an electron mobility of $0.05cm^2/V-sec$, and a current on/off ratio of $I_{ON}/I_{OFF}{\simeq}5{\times}10^4$. Application of bottom-gate voltage stresses, however, increased the interface charges on $MoS_2/SiO_2$, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

Analytical Model of Threshold Voltage for Negative Capacitance Junctionless Double Gate MOSFET Using Ferroelectric (강유전체를 이용한 음의 정전용량 무접합 이중 게이트 MOSFET의 문턱전압 모델)

  • Hakkee Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.36 no.2
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    • pp.129-135
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    • 2023
  • An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔVth of a junctionless double gate MOSFET using ferroelectric-metal-SiO2 as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔVth=0.

Novel Devices for Sub-100 nm CMOS Technology

  • Lee, Jong-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.04b
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    • pp.180-183
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    • 2000
  • Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

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Roles of metabotropic glutamate receptor 5 in low [Mg2+]o-induced interictal epileptiform activity in rat hippocampal slices

  • Ji Seon Yang;Hyun-Jong Jang;Ki-Wug Sung;Duck-Joo Rhie;Shin Hee Yoon
    • The Korean Journal of Physiology and Pharmacology
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    • v.28 no.5
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    • pp.413-422
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    • 2024
  • Group I metabotropic glutamate receptors (mGluRs) modulate postsynaptic neuronal excitability and epileptogenesis. We investigated roles of group I mGluRs on low extracellular Mg2+ concentration ([Mg2+]o)-induced epileptiform activity and neuronal cell death in the CA1 regions of isolated rat hippocampal slices without the entorhinal cortex using extracellular recording and propidium iodide staining. Exposure to Mg2+-free artificial cerebrospinal fluid can induce interictal epileptiform activity in the CA1 regions of rat hippocampal slices. MPEP, a mGluR 5 antagonist, significantly inhibited the spike firing of the low [Mg2+]o-induced epileptiform activity, whereas LY367385, a mGluR1 antagonist, did not. DHPG, a group 1 mGluR agonist, significantly increased the spike firing of the epileptiform activity. U73122, a PLC inhibitor, inhibited the spike firing. Thapsigargin, an ER Ca2+-ATPase antagonist, significantly inhibited the spike firing and amplitude of the epileptiform activity. Both the IP3 receptor antagonist 2-APB and the ryanodine receptor antagonist dantrolene significantly inhibited the spike firing. The PKC inhibitors such as chelerythrine and GF109203X, significantly increased the spike firing. Flufenamic acid, a relatively specific TRPC 1, 4, 5 channel antagonist, significantly inhibited the spike firing, whereas SKF96365, a relatively non-specific TRPC channel antagonist, did not. MPEP significantly decreased low [Mg2+]o DMEM-induced neuronal cell death in the CA1 regions, but LY367385 did not. We suggest that mGluR 5 is involved in low [Mg2+]o-induced interictal epileptiform activity in the CA1 regions of rat hippocampal slices through PLC, release of Ca2+ from intracellular stores and PKC and TRPC channels, which could be involved in neuronal cell death.