• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.83-88
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• 2007

The reliability characteristics of class-E RF power amplifier are studied, based on the degradation of MOSFET electrical characteristics. The class-E power amplifier operates as a switch mode operation to achieve high efficiency. This operation leads to high voltage stress when MOSFET switch is turned-off. The increase in threshold voltage and decrease in nobility caused by high voltage stress leads to a drop in the drain current. In the class-E power amplifier the effects caused by the degradation of MOSFET drain current is a drop of the power efficiency and output power. But the small inductor in the class-E load network allows the reliability to be improved. After $10^{7}\;sec$. the drain current decreases 46.3% and the PAE(Power Added Efficiency) decreases from 58% to 36% when the load inductor is 1mH. But when the load inductor is 1nH the drain current decreases 8.89% and the PAE decreases from 59% to 55%.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.540-543
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• 2004

The stress of MgO thin film, which is used as a dielectric protective layer in AC-PDP, was measured by a laser scanning method. MgO films were deposited bye-beam evaporation on glass substrates with dielectrics layer on them in various deposition temperatures ranging from room temperature to 300 $^{\circ}C$. The compressive stress of MgO films was increased with increasing substrate temperature due to intrinsic stress accumulation, causing the densification of the films. Both firing voltage ($V_f$) and sustaining voltage ($V_s$) were reduced for the higher compressively stressed and densified films. In the other hand, another film properties such as preferred crystallographic orientation and surface roughness seemed not to influence the discharge characteristics of $V_f$ and $V_s$ significantly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1266-1272
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• 2012

An InGaZnO thin film transistor with different gate lengths and widths have been fabricated and their device degradations with device sizes have been also performed after negative gate bias stress. The threshold voltage and subthreshold swing have been decreased with decrease of gate length. However, the threshold voltages were increased with the decrease of gate lengths. The transfer curves were negatively shifted after negative gate stress and the threshold voltage was decreased. However, the subthreshold swing was not changed after negative gate stress. This is due to the hole trapping in the gate dielectric materials. The decreases of the threshold voltage variation with the decrease of gate length and the increase of gate width were believed due to the less hole injection into gate dielectrics after a negative gate stress.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Journal of the Korean Vacuum Society
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• v.13 no.4
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• pp.150-156
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• 2004

Boron nitride thin films were deposited on Si(100) substrate by RF (Radio-frequency) UBM (Unbalanced Magnetron) sputtering system. The effect of working pressure and substrate bias voltage on microstructure and compressive stress of boron nitride thin films has been investigated. In high working pressure, the alignment of hBN laminates increased with substrate bias voltage, in low working pressure, however, it was high in low substrate bias voltage. Compressive stress evolution and surface morphology of deposited BN films are closely related with the alignment of hBN laminates. The cBN phase without high compressive stress could be nucleated on hBN thin film by controlling the alignment of hBN laminates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2509-2515
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• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Journal of IKEEE
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• v.23 no.3
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• pp.962-970
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• 2019

In this paper, the non-isolation, high-efficiency and high-voltage-output DC-DC converter using the self-driven synchronous switch is proposed. The proposed converter achieves high-voltage-output by applying a tapped inductor to the conventional boost DC-DC converter structure, and it reduces the voltage stress of main switch applying the lossless capacitor-diode (LCD) snubber to the switch. And the proposed converter applies the synchronous switch instead of the diode to the output part, and thus it resolves the reverse recovery problem and achieves high-efficiency. The synchronous switch of proposed converter uses the self-driven method and has a simple structure. In this paper, the operation principle of proposed converter is explained, and then, a design example of the converter prototype is presented. And the characteristics of the proposed converter are shown through experimental results of the prototype made with the designed circuit parameters.

• Electrical & Electronic Materials
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• v.8 no.3
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• pp.357-361
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• 1995

An experiment on characteristics of nMOSFET's in the long stress condition with the maximum of the substrate current has been carried out in order to study on the degradation due to the hot-carrier effect. Based on the measured result of the threshold voltage, the damage is mostly due to the hole injection into the oxide. After long stress, it was shown that the drain current increased at low gate voltages and hence decreased at high gate voltages.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.343-349
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• 2005

This paper proposes a novel zero-voltage-switching (ZVS) Push-pull DC-DC Converter for high input voltage and high power applications. This topology utilizes two switches in series to replace one switch in conventional push-pull converter, and two clamping diodes are introduced. The voltage stress of the switches is the input voltage, and the switches can realize ZVS with the use of the leakage inductance of the transformer. Furthermore, secondary full-wave rectifier with a clamping capacitor is used to eliminate the voltage oscillation and spike of the rectifier diodes due to the reverse recovery. Therefore, the electromagnetic interference is reduced effectively. The operation principle of the proposed converter is analyzed theoretically. The output characteristic, ZVS condition and design principle of the clamping capacitor are discussed. Experimental results obtained from a 270V input 2kW prototype with $95.8\%$ high efficiency confirms the design.