• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.46-52
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• 1994

DC and AC current crowding effects for microwave and high speed bipolar transistors are investigated in detail using a new and accurate measurement technique based on Z-parameter equationa. Using the new measurement technique dc and ac current crowding effects have been explained clearly in bipolar junction transistors. To model ac crowding effects a capacitive element defined as base capacitance (C$_b$), called ac crowding capacitance is added to base resistance in parallel thereby treating the base resistance(R$_b$) as base impedance Z$_b$. It is shown that base resistance decreases with increasing collector current due to dc current crowding and approaches to a certain limited value at high collector current due to current crowding and approaches to a certain limited value at high collector currents regardless of the emitter size. It is also observed that due to ac current crowding base capacitance increases with increasing collector current. To quantigy the ac crowding effects for SPICE circuit simulation the base capacitance(C$_b$) including the base depletion and diffusion components has been modeled with an analytical expression form.

• The Korean Journal of Food And Nutrition
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• v.34 no.1
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• pp.26-35
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• 2021

Myrosinases (thioglucosidases) catalyze the hydrolysis of a class of compounds called glucosinolates, of which the aglycones show various biological functions. It is often necessary to minimize the loss of myrosinase activity during thermal processing of cruciferous vegetables. Myrosinase was isolated from a popular spice, white mustard (Sinapis alba), and its thermal inactivation kinetics was investigated. The enzyme was extracted from white mustard seeds and purified by a sequential processes of ammonium sulfate fractionation, Concanavalin A-Sepharose column chromatography, and gel permeation chromatography. At least three isozymes were revealed by Concanavalin A-Sepharose column chromatography. The purity of the major myrosinase was examined by native polyacrylamide gel electrophoresis and on-gel activity staining with methyl red. The molecular weight of the major enzyme was estimated to be 171 kDa. When the consecutive step model was used for the thermal inactivation of the major myrosinase, its inactivation energy was 44.388 kJ/mol for the early stage of destruction and 32.019 kJ/mol for the late stage of destruction. When the distinct two enzymes model was used, the inactivation energy was 77.772 kJ/mol for the labile enzyme and 95.145 kJ/mol for the stable enzyme. The thermal inactivation energies lie within energy range causing nutrient destruction on heating.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.719-729
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• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Journal of IKEEE
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• v.20 no.2
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• pp.163-166
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• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.174-177
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• 2003

본 논문에서는 AC PDP의 유지방전구간에서의 인가전압에 따른 방전전류, 공간전압, 벽전하 등의 변화를 새로운 AC PDP를 위한 등가회로모델을 사용하여 효율적이고 간편하게 시뮬레이션 한 결과를 소개한다. 벽전하의 정확한 분석은 안정적이고 효율적인 AC PDP의 구동 방법을 개발하기 위해 계속 연구, 보고 되어 왔지만, 인가되는 전압의 변화에 따른 시간적인 셀 내부의 변화를 빠르고 편리하게 분석하고 이해하는데 효과적인 방법은 제시되지 못하였다. 본 논문에서는 AC PDP의 전극간 물리적인 특성을 고려하여 3개의 직렬 커패시터와 1개의 병렬 커패시터, 2개의 싸이리스터를 사용하여 AC PDP를 위한 등가회로모델을 구성하여 제시하였다. 제안된 등가회로모델은 SPICE와 같은 표준 회로시뮬레이션 툴에 손쉽게 적용가능하며, 이러한 방법으로 분석된 패널내의 전류, 공간전압, 벽전하의 동특성을 소개하였다. 등가회로모델을 이용한 시뮬레이션 결과는 실험을 통한 측정 결과와 비교하여 그 정확성을 검증하였다. 인가전압의 시간적 변화의 따른 유입전류 및 셀 내의 전압 및 전하의 분포를 손쉽고 정확하게 시뮬레이션 할 수 있는 본 AC PDP의 등가회로모델은 AC PDP의 특성을 이해하는 데에 중요한 도구가 될 것이며 효율적인 구동 방식의 개발 및 분석 등에 널리 활용될 수 있을 것이다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.173-183
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• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.13-20
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• 2003

The model of the transistor saturation current of the BJT for integrated circuits based upon the semiconductor physics is proposed. The method for calculating the doping profile in the base region using process conditions is presented and the method for calculating the base Gummel number of lateral PNP BJT and vertical NPN BJT is proposed. The transistor saturation currents of NPN BJT using 20V and 30V process conditions obtained from the proposed method show an average relative error of 6.7% compared with the measured data and the transistor saturation currents of PNP BJT show an average relative error of 6.0% compared with the measured data.