• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.270-274
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• 2011

This paper presents a parameterized simulation program with integrated circuit emphasis (SPICE) model of a two-level microbolometer based on negative-temperature-coefficient thin films, such as vanadium oxide or amorphous silicon. The proposed modeling begins from the electric-thermal analogy and is realized on the SPICE modeling environment. The model consists of parametric components whose parameters are material properties and physical dimensions, and can be used for the fast design study, as well as for the co-design with the readout integrated circuit. The developed model was verified by comparing the obtained results with those from finite element method simulations for three design cases. The thermal conductance and the thermal capacity, key performance parameters of a microbolometer, showed the average difference of only 4.77% and 8.65%, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.1012-1015
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• 1992

A gate-turn-off thyristor (GTO) that has a fuction of self-commutation is a device that can be turned on like a thyristor with a single pulse of gate current and turned-off by injecting a negative gate current pulse. GTOs have been in existence almost from the beginning of thyristor era, recently are these devices being developed with large power-handling capabilities and improved performance, and they are gaining popularity In conversion equipment. In this paper, the effects of internal parameters of GTO model using a circuit containing two transistors and three resistors the switching operation and the turn-off snubber characteristics is investigated using SPICE program.

• 조명전기설비학회논문지
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• 제14권2호
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• pp.43-45
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• 2000

본 연구에서는 BICMOS 공정으로 제조된 바이폴라 프렌지스터의 SPICE 잡음 파라미터 추출방법을 제시하였다. 기하학적 분석요로부터 $K_f$ 값이 에미터 면적에 반비례하고 있음을 보였다. 그리고 $K=0.8\times10_{-20}, A_f=2, \alpha=1$ 값이 추출되었다.

• 한국산학기술학회논문지
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• 제13권12호
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• pp.6046-6051
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• 2012

본 논문에서는 암호화 통신응용을 위한, 트랜스콘덕터에 기반한 비선형 저항으로 이루어진 카오스 추아회로를 구현하였다. 제안하는 회로는 인덕터와 커패시터의 수동소자와, MOS 트랜지스터 기반 가변저항 및 트랜스콘덕터 기반 추아 다이오드로 이루어진다. 제안하는 회로는 SPICE 모의실험결과, 시간파형, 위상특성 및 주파수 해석 등을 통하여 다양한 카오스 다이나믹스를 보여주었다.

• 전자공학회논문지A
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• 제31A권1호
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• pp.39-47
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• 1994

The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

• 전자공학회논문지D
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• 제36D권1호
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• pp.1-7
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• 1999

본 논문에서는 마이크로 스트립 다중 전송 선로의 고속 디지털 펄스 신호에 대한 상호 결합 특성을 시간영역에서 해석하기 위해 FDTD법을 사용하였고, SPICE에 의한 결과 및 측정결과와 상호 비교하였다. 기존 SPICE에 의한 다중 전송 선로의 해석은 FDTD법에 비해 정확도가 저하되고, 손실 특성에 대한 해석을 할 수 없으므로, 본 논문에서는 FDTD법을 이용하여 무손실 및 손실을 고려한 다중 전송 선로의 디지털 전송 특성을 해석하고 누화 특성을 비교하여 나타냈다.

• 한국전기전자재료학회논문지
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• 제28권3호
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• pp.154-159
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• 2015

In this paper, we propose a numerical method to model temperature dependent threshold voltage shift observed in metal oxide thin-film transistors (TFTs). The proposed model is then implemented in AIM-SPICE circuit simulation tool. The proposed method consists of modeling the well-known stretched-exponential time dependent threshold voltage shift and their temperature dependent coefficients. The outputs from AIM-SPICE tool and the stretched-exponential model at different temperatures in the literature are compared and they show a good agreement. Since metal oxide TFTs are the promising candidate for flat panel displays, the proposed method will be a good stepping stone to help enhance reliability of fast-evolving display circuits.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.686-691
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• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor. Proposed chaotic circuit consist of L, C, R and transcondcutor based Chua's diode. We performed SPICE simulation for chaotic dynamics such as time seriesform, frequency analysis and phase plane of the circuit. Chaotic dynamics of the circuit was analysed according to MOS size variation of the operational transconductance amplifier. Also, we performed SPICE circuit analysis for temperature dependance of the circuit. SPICE results showed that chaotic dynamics of the circuit varied according to the temperature variation and chaotic signals were generated in specific temperature conditions.

• 전자공학회논문지
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• 제49권12호
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• pp.173-178
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• 2012

RF 직접 추출 방법을 통해 얻은 정확한 MOSFET 기판 파라미터를 이용하여 기판저항만을 가진 BSIM4 모델은 스케일링 부정확성 때문에 넓은 영역의 게이트 길이에 적용하기에는 물리적으로 맞지 않다는 것이 증명됐다. BSIM4의 비물리적인 문제점을 제거하기 위해서 추가적인 유전체 기판 캐패시터를 가진 수정된 BSIM4 모델이 사용되었고, 이 모델의 물리적 타당성은 우수한 게이트 길이 scalability를 관찰함으로써 증명되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.391-392
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• 2008

A SPICE-based 3-dimensional circuit model of Light-Emitting Diode(LED) was modified include the reverse breakdown properties. The new model is found to be accurate to study the failure mechanisms of LEDs under electrostatic discharge (ESD) and electronic overstress (EOS). It was found that the permanent damages under heavy reverse stress is mainly due to the high electric field strength in P-GaN layer.