• Title/Summary/Keyword: source/drain

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Analysis of Drain Induced Barrier Lowering for Double Gate MOSFET According to Channel Doping Concentration (채널도핑강도에 대한 이중게이트 MOSFET의 DIBL분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.3
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    • pp.579-584
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    • 2012
  • In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping concentration.

Operation characteristics of IGZO thin-film transistors (IGZO 박막트랜지스터의 동작특성)

  • Lee, Ho-Nyeon;Kim, Hyung-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.5
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    • pp.1592-1596
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    • 2010
  • According to the increase of the channel length with fixed width/length, characteristic curves of drain current as a function of gate bias voltage of indium gallium zinc oxide (IGZO) thin-film transistors moved to a positive direction of gate voltage, and field-effect mobility decreased. In case of fixed length and width of channel, field-effect mobility was lower and subthreshold slope was larger when drain bias voltage was higher. Due to large work function of IGZO, band bending at the junction region between IGZO channel and source/drain electrodes was expected to be in opposite direction to that between silicon and metal electrodes; this could explain the above results.

Analysis of Drain Induced Barrier Lowering for Double Gate MOSFET According to Channel Doping Intensity (채널도핑강도에 대한 DGMOSFET의 DIBL분석)

  • Jung, Hak-Kee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.888-891
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    • 2011
  • In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.

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An Experimental Study on the Noise Characteristics of Water Supply and Drain Installations Varied with Water Suppling Pressure in Apartment Bathroom (급수압 변화에 따른 대변기와 세면기의 급배수 소음 특성에 관한 실험적 연구)

  • Lee, Tai-Gang;Ko, Kwang-Pil;Choi, Eun-Suk;Kim, Hang;Kim, Sun-Woo
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.17 no.3 s.120
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    • pp.226-234
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    • 2007
  • This study aims to evaluate noise emission from water supply and drain installations in apartment bathroom. These noise were one of the most annoying noise sources in apartment houses. Especially, drain plumbing system have used bellow bathroom ceiling, it was very discomfort to hear the noise in bellow apartment. Noise of closets and faucets were measured which were main noise source, then these noise were evaluate and analyzed the emitting characteristics varying the supplying water pressure. As increasing the water pressure, also total noise level of the water supplying stool noise and faucet noise were increased. Especially the water closet showed remarkably the increasing noise level in middle and high frequency bandwidth, while the noise level of faucets increased in $50\;Hz{\sim}250\;Hz$ of low frequency bandwidth. Vortex closet were favorable to syphon closet, and lever faucet were favorable to conventional lavatory faucet on reducing the noise. Above these results could be used in basic data establishing KS (Korean Standard) for evaluation and rating procedure and measures reducing these noise.

Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 도핑분포함수에 따른 DIBL)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2643-2648
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    • 2015
  • This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

Numerical Analysis on Consolidation of Soft Clay by Sand Drain with Heat Injection (수치해석을 통한 샌드드레인과 열주입에 의한 연약지반의 압밀 해석)

  • Koy, Channarith;Yune, Chan-Young
    • Journal of the Korean Geotechnical Society
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    • v.33 no.11
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    • pp.45-57
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    • 2017
  • Temperature change affects consolidation behavior of soft clays. The increase of temperature in soft clays induces the increase of pore water pressure. The dissipation of the excess pore water pressure decreases volume and void ratio. Also, the consolidation rate is accelerated by high temperature which induces the decrease of viscosity of pore fluid. The effects of temperature on the consolidation behavior such as consolidation settlement, consolidation time, and pore water pressure were investigated in this study. A numerical analysis of hydro-mechanical (HM) and thermo-hydro-mechanical (THM) behavior was performed. The combination of heat injection and sand drain for consolidating the soft ground, with varying temperature (40 and $60^{\circ}C$) and sand drain diameter (40, 60, and 80 mm), was considered. The results show that the temperature inside soil specimen increases with the increase of the temperature of heating source and the diameter of sand drain. Moreover, the heat injection increases the excess pore water pressure and, accordingly, induces additional settlement in overconsolidated (OC) state and reduces the consolidation time in normally consolidated (NC) state.

Organic field-effect transistors with step-edge structure

  • Kudo, Kazuhiro
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.91-93
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    • 2008
  • The organic field-effect transistors with step-edge structure were fabricated. Source and drain electrodes were obliquely deposited by vacuum evaporation. The step-edge of the gate electrode serve as a shadow mask, and the short channel is formed at the step-edge. The excellent device performances were obtained.

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Analysis of electron mobility in LDD region of NMOSFET (NMOSFET에서 LDD 영역의 전자 이동도 해석)

  • 이상기;황현상;안재경;정주영;어영선;권오경;이창효
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.123-129
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    • 1996
  • LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

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Reduction of Source/Drain Series Resistance in Fin Channel MOSFETs Using Selective Oxidation Technique (선택적 산화 방식을 이용한 핀 채널 MOSFET의 소스/드레인 저항 감소 기법)

  • Cho, Young-Kyun
    • Journal of Convergence for Information Technology
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    • v.11 no.7
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    • pp.104-110
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    • 2021
  • A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.