• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1357-1359
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• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.310-310
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• 2013

본 연구에서는 Titanium (Ti) source/drain 전극 접합이 차세대 비정질 InGaZnO (IGZO) 기반 박막형 트랜지스터에 미치는 영향을 화학적, 구조적, 전기적 특성 분석을 통하여 관찰하고 Ti/IGZO 접합 특성을 설명할 수 있는 메커니즘을 제시하였다. IGZO 기반 박막형 트랜지스터 소자의 구동 특성은 transmission line method (TLM) 패턴 공정을 이용하여 정량적으로 분석되었다. 비정질 IGZO 기반의 박막형 트랜지스터에서 Ti source/drain 전극 접합에 의한 구동 특성 변화 및 영향을 확인하기 위하여 금속/산화물 계면 반응성이 낮은 silver (Ag) source/drain 전극이 reference로 비교되었으며, 그 결과 Ti source/drain 전극 접합이 적용된 비정질 IGZO 트랜지스터의 경우 Ti 금속과 IGZO 산화물 계면에 형성되는 열역학적으로 안정한 $TiO_x$ 층의 형성에 의해 VT ($-{\Delta}0.52V$) shift 및 saturation mobility ($8.48cm^2$/Vs) 상승됨을 확인하였다. 뿐만 아니라 TLM 패턴을 이용한 IGZO 트랜지스터의 전기적 변수 도출 및 수치적 해석으로부터 $TiO_x$ 계면층 형성이 Ti 금속과 비정질 InGaZnO 계면에서의 effective contact resistivity를 효과적으로 낮출 수 있음을 확인하였다. Ti source/drain 전극 접합에 의해 발생되는 $TiO_x$ 계면층의 화학적, 구조적 특성과 $TiO_x$ 계면층 생성에 의한 소자 특성 변화를 연관시켜 해석함으로써, IGZO 기반 박막형 트랜지스터에서의 Ti source/drain 전극 접합이 비정질 IGZO 기반 박막형 트랜지스터에 미치는 영향을 설명하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.271-272
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• 2007

Displacement current $(I_{dis})$ and drain-to-source current $(I_{DS})$ are evaluated using the simultaneous measurements of source $(I_S)$ and drain $(I_D)$ currents during the application of a constant drain voltage and a triangular-wave gate voltage $(V_{GS})$ to top-contact pentacene thin-film transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.715-718
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• 2003

본 논문에서는 MOSFET source/drain 고체 확산 원으로써 도핑된 폴리 실리콘을 사용하였으며 확산 후 남은 폴리 실리콘은 elevated source/drain 역할을 하여 저항을 줄여 준다. 또한 제안 된 구조는 게이트 절연막 공정 이전에 확산 공정이 이루어 지기 때문에 후속 열처리에 취약한 고유전율 게이트 절연막 공정과 금속 게이트 공정에 적합한 공정으로 적합함을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.384-385
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• 2006

We studied about conductive pastes of the source-drain contacts for OTFTs(organic thin-film transistors) fabricated by direct printing(screen printing) method. We used Ag and conductive carbon black powder as the conductive fillers of pastes. The conductive pastes were manufactured by various dispersing agents and dispersing conditions and source-drain contacts with $100{\mu}m$ of channel length were fabricated. We could obtain the OTFTs which exhibited different field-effect behaviors over a range of source-dram and gate voltages depending on a kind of conductive fillers used conductive pastes.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.303-306
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• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.