• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권1호
• /
• pp.52-58
• /
• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 한국전기전자재료학회논문지
• /
• 제16권1호
• /
• pp.5-10
• /
• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Journal of Korean Vacuum Science & Technology
• /
• 제6권1호
• /
• pp.12-15
• /
• 2002

The physical properties, including magneto-optical and transport ones, of Ni$_2$MnG$_2$ alloy in the martensitic and austenitic states were investigated. The dependence of the temperature coefficient of resistivity on temperature shows kinks at the structural and ferro-para magnetic transitions. Electron-magnon and electron-phonon scattering are analyzed to be the dominant scattering mechanisms of the Ni$_2$MnG$_2$ alloy in the martensitic and austenitic states, respectively. The experimental real parts of the off-diagonal components of the dielectric function present two sharp peaks, one at 1.9 eV and the other at 3.2 eV, and a broad shoulder at 3.5 eV, all are identified by the band-structure calculations. These peak positions are coincident with those in the corresponding optical-conductivity spectrum, which is thought to originate from the single-spin state in Ni$_2$MnG$_2$ alloy.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.80-83
• /
• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
• /
• pp.3-4
• /
• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• 전자공학회논문지D
• /
• 제36D권10호
• /
• pp.23-30
• /
• 1999

본 논문에서는 전자선 직접 묘화 시스템을 이용하여 50 nm 이하의 패턴 폭을 가지는 패터닝 결과를 얻기 위한 실험을 수행하였다. SAL601 negative E-beam PR(Photo Resist)를 이용하여 실험을 진행하였고, E-beam 장비의 특성을 최대로 이용하기 위해서 PR의 두께를 100nm로 줄이고, field 크기를 200 ${um}m$로 줄여 실험하였으며, 또한 SAL601 PR의 경우 작은 선폭을 얻기 위해 중요한 요인 중에 하나인 PEB (Post Expose Bake) 온도와 시간을 줄이면서 실험을 진행하였다. 여기에 디지타이징 방식의 최적화를 통하여 50 nm 이하의 패턴 폭을 가지는 단선 패터닝 결과를 얻었다. 이 공정을 이용하여 단전자 메모리 소자에 응용 가능한 50 nm 급의 silicon 양자선과 silicon 양자점을 제작하였다. 이는 현재 많이 연구되고 있는 단전자 기억소자 및 국소 채널 MOS소자 제작에 유용할 것이다.

• 한국전기전자재료학회논문지
• /
• 제19권4호
• /
• pp.314-321
• /
• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국컴퓨터산업학회논문지
• /
• 제6권5호
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Astronomy and Space Sciences
• /
• 제22권4호
• /
• pp.537-558
• /
• 2005

본 논문에서는 HAUSAT-2위성이 운용될 케도의 우주 방사능 환경 및 총 피폭효과(Total Ionizing Dose), 단일사건 효과(Single Event Effects) 등에 대해 분석하였다. 총 피폭효과에 영향을 미치는 우주 방사능은 포획된 양성자, 전자, 태양 양성자 및 우주선이다. 총 피폭효과는 선량 심도선 분석을 통해 해석을 수행하였으며, DMBP(Design Margin Breakpoint) 방법과 3-D 구분구적법을 이용하여 HAVSAT-2의 부품의 총 피폭량에 대한 내성을 검증하였다. 단일사건 효과에 대하여 위성체 외부와 내부 방사능 환경으로 양성자와 중이온에 대하여 선형에너지 전달량(LET) 스펙트럼을 분석하였으며, HAUSAT-2의 전자소자로 사용예정인 MPC860T2B 마이크로프로세서와 메모리 K6X8008T2B에 대한 SEU(Single Event Upset) 및 SEL(Single Event Latch-up) 발생률을 추정하였다. 분석 결과 SEU는 운용 중에 수차례 발생하며 SEL 발생은 임무기간동안 일어나지 않을 것으로 추정되었다. HAUSAT-2는 소프트웨어 해밍코드 EDAC을 이용하여 SEU 발생에 대처할 수 있는 시스템 레벨의 설계를 반영하였다. 이 연구에서 수행된 방사능 해석은 ESA의 SPENVIS소프트웨어를 이용하였다.

• Journal of Ginseng Research
• /
• 제47권3호
• /
• pp.448-457
• /
• 2023

Background: Alzheimer's disease (AD) is a common form of dementia, and impaired mitophagy is a hallmark of AD. Mitophagy is mitochondrial-specific autophagy. Ginsenosides from Ginseng involve in autophagy in cancer. Ginsenoside Rg1 (Rg1 hereafter), a single compound of Ginseng, has neuroprotective effects on AD. However, few studies have reported whether Rg1 can ameliorate AD pathology by regulating mitophagy. Methods: Human SH-SY5Y cell and a 5XFAD mouse model were used to investigate the effects of Rg1. Rg1 (1µM) was added to β-amyloid oligomer (AβO)-induced or APPswe-overexpressed cell models for 24 hours. 5XFAD mouse models were intraperitoneally injected with Rg1 (10 mg/kg/d) for 30 days. Expression levels of mitophagy-related markers were analyzed by western blot and immunofluorescent staining. Cognitive function was assessed by Morris water maze. Mitophagic events were observed using transmission electron microscopy, western blot, and immunofluorescent staining from mouse hippocampus. The activation of the PINK1/Parkin pathway was examined using an immunoprecipitation assay. Results: Rg1 could restore mitophagy and ameliorate memory deficits in the AD cellular and/or mouse model through the PINK1-Parkin pathway. Moreover, Rg1 might induce microglial phagocytosis to reduce β-amyloid (Aβ) deposits in the hippocampus of AD mice. Conclusion: Our studies demonstrate the neuroprotective mechanism of ginsenoside Rg1 in AD models. Rg1 induces PINK-Parkin mediated mitophagy and ameliorates memory deficits in 5XFAD mouse models.