• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.1
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• pp.12-15
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• 2002

The physical properties, including magneto-optical and transport ones, of Ni$_2$MnG$_2$ alloy in the martensitic and austenitic states were investigated. The dependence of the temperature coefficient of resistivity on temperature shows kinks at the structural and ferro-para magnetic transitions. Electron-magnon and electron-phonon scattering are analyzed to be the dominant scattering mechanisms of the Ni$_2$MnG$_2$ alloy in the martensitic and austenitic states, respectively. The experimental real parts of the off-diagonal components of the dielectric function present two sharp peaks, one at 1.9 eV and the other at 3.2 eV, and a broad shoulder at 3.5 eV, all are identified by the band-structure calculations. These peak positions are coincident with those in the corresponding optical-conductivity spectrum, which is thought to originate from the single-spin state in Ni$_2$MnG$_2$ alloy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.23-30
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• 1999

We experimented on the sub 50nm patterning using E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of E-beam system, firstly, we reduced the PR thickness to 100nm, and the field size to 200 ${um}m$. Then PEB (Post Expose Bake) time/temperature, which is one of the very important factors when SAL601 is used, were reduced for minimum line width. In addition, digitizing is optimized for better results. Quantum wire and quantum dot which can be used for nanoscale memory device, such as single electron memory device, are fabricated using these developed lithography techniques.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Astronomy and Space Sciences
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• v.22 no.4
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• pp.537-558
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• 2005

This paper addresses the results of HAUSAT-2 radiation environment and effect analyses, including TID and SEE analyses. Trapped proton and electron, solar proton, galactic cosmic ray models were considered for HAUSAT-2 TID radiation environment analysis. TID was analyzed through total dose-depth curve and the radiation tolerance of TID for HAUSAT-2 components was verified by using DMBP method and sectoring analysis. HAUSAT-2 LET spectrum for heavy ion and proton were also analyzed for SEE investigation. SEE(SEU, SEL) analyses were accomplished for MPC860T2B microprocessor and K6X8008T2B memory. It was estimated that several SEUs may occur without SEL during the HAUSAT-2 mission life(2 years). Software Hamming Code EDAC has been implemented to detect and correct the SEU. In this study, all radiation analyses were conducted by using SPENVIS software.

• Journal of Ginseng Research
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• v.47 no.3
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• pp.448-457
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• 2023

Background: Alzheimer's disease (AD) is a common form of dementia, and impaired mitophagy is a hallmark of AD. Mitophagy is mitochondrial-specific autophagy. Ginsenosides from Ginseng involve in autophagy in cancer. Ginsenoside Rg1 (Rg1 hereafter), a single compound of Ginseng, has neuroprotective effects on AD. However, few studies have reported whether Rg1 can ameliorate AD pathology by regulating mitophagy. Methods: Human SH-SY5Y cell and a 5XFAD mouse model were used to investigate the effects of Rg1. Rg1 (1µM) was added to β-amyloid oligomer (AβO)-induced or APPswe-overexpressed cell models for 24 hours. 5XFAD mouse models were intraperitoneally injected with Rg1 (10 mg/kg/d) for 30 days. Expression levels of mitophagy-related markers were analyzed by western blot and immunofluorescent staining. Cognitive function was assessed by Morris water maze. Mitophagic events were observed using transmission electron microscopy, western blot, and immunofluorescent staining from mouse hippocampus. The activation of the PINK1/Parkin pathway was examined using an immunoprecipitation assay. Results: Rg1 could restore mitophagy and ameliorate memory deficits in the AD cellular and/or mouse model through the PINK1-Parkin pathway. Moreover, Rg1 might induce microglial phagocytosis to reduce β-amyloid (Aβ) deposits in the hippocampus of AD mice. Conclusion: Our studies demonstrate the neuroprotective mechanism of ginsenoside Rg1 in AD models. Rg1 induces PINK-Parkin mediated mitophagy and ameliorates memory deficits in 5XFAD mouse models.