• Journal of Institute of Control, Robotics and Systems
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• v.7 no.6
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• pp.550-557
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• 2001

There are several applications and error analysis methods using GPS(Global Positioning System) In most analysis positioning and timing errors are represented as the multiplication of DOP(Dilution Of Precision) and measurement errors, which are affected by the receiver and measurement type. Therefore, lots of DOPs are defined and used to analyze and predict the performance of positioning and timing systems. In this paper, the relationships between these DOPs are investigated in detail, The relationships between GDOP(Geometric DOP), PDOP(Position DOP) and TDOP(Time DOP) in the absolute positioning are de-rived. Using these relationships, the affect of clock bias is analyzed. The relationships between RGDOP(Relative DOP) and PDOP are also derived in relative positioning where the single difference and double dif-ference techniques are used. From the results, it is expected that using the common clock will give better performance when the single difference technique is used while the effects of clock is eliminate when the double difference technique is used. Finally, the error analyses of dual frequency receivers show that the narrow lane measurements give more accurate results than wide line of or L1. L2 independent measurements.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.48-55
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• 2017

This paper proposes a new link structure that transmits power, clock, and data through a single optical fiber for a future automotive network. A pulse-position modulation (PPM) technique is adopted to guarantee a DC-balanced signal for robust power transmission regardless of transmitted data pattern. Further, circuit implementations and theoretical analyses for the proposed PPM transceiver are described in this paper. A prototype transceiver fabricated in 65-nm CMOS technology, is used to verify the PPM signaling part of the proposed system. The prototype achieves a $10^{-13}$ bit-error rate and 0.188-UI high frequency jitter tolerance while consuming 14 mW at 800 Mb/s.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1850-1851
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.50-56
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• 1999

This paper presents a new technique for generating precise clock delays. The technique can obtain finer timing resolution less than the gate delay of the delay chain by locking in multiple clock period. Using this technique, a 250ps of timing resolution could be achieved from a 750ps delay of the single delay stage in a DLL(Delay Locked Loop) structure. The delay chain of the proposed circuit is locked on three times of the clock period and a finer delay resolution than the absolute gate delay is achieved and verified through the simulation.

• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1055-1061
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• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.