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Retiming for SoC Using Single-Phase Clocked Latches  

Kim Moon-Su (Semiconductor, Samsung Electronics)
Rim Chong-Suck (Department of Computer Science, Sogang)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.9, 2006 , pp. 1-9 More about this Journal
Abstract
In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.
Keywords
SoC; retiming; wire pipelining; timing analysis; fixpoint computation;
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