• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.129-132
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• 2001

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.206-212
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• 2007

In this paper, a novel power/ground plane using the hybrid-cell electromagnetic band-gap(EBG) structure is proposed for the wide-band suppression of the ground bound noise(GBN) or simultaneous switching noise(SSN). The -30 dB stopband of the proposed structure starts from a few hundred MHz where the GBN/SSN energy is dominant. The distinctive features of this new structure are the thin spiral strip line and hybrid-cells. They realize the enhanced inductance and the shorter period of the EBG lattice. As a result, the lower cut-off frequency and bandwidth of the -30 dB stopband becomes lower and wider, respectively. In addition, the proposed structure has smaller number of resonance modes between power/ground planes and performs a low EMI behavior compared with the reference board.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.62-70
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• 2006

This paper presents a new power plane design method incorporating a single geometry derived from a unit cell of photonic bandgap(PBG) structure. This method yields constantly wide suppression of parallel plate resonances from 0.9 GHz to 4.2 GHz and is very efficient to eliminate PCB resonances in a specified frequency region to provide effective suppression of simultaneous switching noise(SSN). It is shown that with only two cells the propagation of unwanted high frequency signals is effectively suppressed, while it could provide continuous return signal path. The measured results agree very well with theoretically predicted ones, and confirm that proposed method is effective for reducing EMI, with measured near-field distribution. The proposed topology is suitable for design of high speed digital system.

• ETRI Journal
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• v.32 no.2
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• pp.265-272
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• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.334-337
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• 2007

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1145-1148
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• 2003

SSN을 줄이기 위해 벌크단의 그라운드와 소스단의 그라운드를 분리한다. 이 방법을 사용하면 소스과 벌크의 전압 차이가 발생하는데 소스에 발생되는 전압은 기생인덕턴스로 인해 노이즈 전압이되고 벌크의 전압은 그라운드에 바로 연결되기 때문에 0V가 된다. 이 방법을 사용하면 소스단에 기생인덕턴스가 벌크단에 미치지 못하게 되어 노이즈를 줄일 수 있다.. 본 논문에서 나타난 결과는 공통그라운드를 사용한 구동 드라이버 보다 SSN을 10% 간단히 줄일수 있다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.786-795
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• 2010

In this paper, we propose a new EBG structure that the two unit cells are connected by the bridge line in signal transmission plane. The SSN of the power plane is reduced effectively by via holes and bridge lines connecting the unit cells. The superior signal transfer characteristic is shown between the signal lines in the signal transmission plane. The proposed EBG structure contains 1.2 GHz cut-off frequency and less than －30 dB suppression in the 8.3 GHz broad bandwidth. In addition, To improve the SI(Signal Integrity) in signal transmission plane keeping the same bandstop frequency range, the optimized location of the reference plane is proposed.