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http://dx.doi.org/10.5573/JSTS.2007.7.4.235

A SSN-Reduced 5Gb/s Parallel Transmitter  

Lee, Seon-Kyoo (Department of Electrical Engineering, Pohang University of Science and Technology)
Kim, Young-Sang (Department of Electrical Engineering, Pohang University of Science and Technology)
Park, Hong-June (Department of Electrical Engineering, Pohang University of Science and Technology)
Sim, Jae-Yoon (Department of Electrical Engineering, Pohang University of Science and Technology)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.7, no.4, 2007 , pp. 235-240 More about this Journal
Abstract
A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.
Keywords
Simultaneous switching noise; inversion coding; parallel link; memory interface;
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