• ETRI Journal
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• v.23 no.3
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• pp.106-110
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• 2001

Subpicosecond all-optical switching method based on the simultaneous two-photon coherence exchange is proposed and numerically demonstrated. The optical switching mechanism is based on the optical field induced dark resonance swapping via nondegenerate four-wave mixing processes. For potential applications of ultrafast all-optical switching in fiber-optic communications, 10-THz channel number independent quantum router is discussed.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1084-1087
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• 2000

This paper presents a new approach to evaluate the maximum number of simultaneous switching gates of a given combinational circuit. The new approach is based on an iterative method proposed by Sinogi et al. and applies a simulated annealing strategy to search jot a new solution. The experimental evaluation using ISCAS’85 benchmark circuits shows that the proposed approach has attained an excellent improvement compared with other rotated methods including the iterative method.

• Korean Journal of Food Science and Technology
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• v.37 no.6
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• pp.1024-1027
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• 2005

Rapid and simple method was developed for simultaneous determination of vitamins $D_3\;and\;K_1$ contents in infant formula. Contents of vitamins $D_3\;and\;K_1$, extracted by column-switching HPLC with reversed phase column using enzymatic hydrolysis and organic solvent, in CRM determined by developed method were within certified ranges of standard values.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.409-412
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• 1990

Series connection of power switching semiconductor elements is unavoidable when a high voltage convertor is aimed. However, it is important to equalize distribution of turn-off voltage because the switching elements have different characteristics. In this paper optimal switching control algorithm is proposed so that series connected poker switching semiconductor elements can be always switched simultaneous turn-on and turn-off.

• ETRI Journal
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• v.32 no.2
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• pp.265-272
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• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.6
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• pp.862-867
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• 1995

In this paper a method to perform Exclusive-OR operation between two tabular type Boolean expressions is presented. The proposed method allows to solve the switching equations and the simultaneous equations in a rather direct manner, compared with Unger's method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.79-84
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• 2008

Switching speeds increase in both frequency and the transition rate of edges. Inadequate forecast for simultaneous switching signals may cause designing the power planes without sufficient current capability. The delay of critical signals in a chip can be therefore inadvertently increased and the situation makes it hard to debug issues. It is important to find the degree of increased switching during the debugging or chip characterization phases. This paper proposes the interpolation method to predict the switching density in a design. The interpolation was achieved by utilizing the dependencies between switching frequency and the delay appeared in a ring oscillator. The ring oscillator was primarily used to accumulate the effects of the ground bounce by higher switching. The result of interpolation was demonstrated using DongBu Hitec 0.18um CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.141-144
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• 2002

We present current limiting properties of 1.2kV/70A superconducting fault current limiter based on YBCO thin films. This is consisted of 6 wafers (3 parallel ${\times}$ 2 serial connection) with 4 inch-diameter YBCO thin film. The quench current Iq of the switching elements vary between 33.9 and 35.6 A. Within the difference of 0.5 A in the sum of quench current Iq in two stacks, the serial connection of the stacks showed the simultaneous quench behavior in applied power of 1.2 kV /70 A.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.51-54
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• 2000

This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use ａ-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.