Estimation of Maximum Simultaneous Switching Noise for Ground Interconnection Networks in CMOS Systems

CMOS그라운드 연결망에서의 최대 동시 스위칭 잡음 해석 방법

This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use ａ-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.