• 대한기계학회논문집
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• 제16권12호
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• pp.2298-2305
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• 1992

본 연구에서는 보의 종방향 강성치를 실제보다 훨씬 작은 횡방향 강성치 수준 으로 낮추어 시간 적분을 수행하는 대신, 종방향에 작용하는 힘을 분산시켜서 계산시 종방향 상대 변형을 억제하는 기법을 사용하였다. 또 여러개의 물체가 조인트에서 서로 연결되어 이루어진 다물체 도역학의 해는 운동 방정식과 기구학적 제한조건을 모 두 만족시켜야 하며, 상미분 방정식 해법용 시간 적분을 바로 적용할 수는 없다. 본 논문에서는 참고문헌(13)과 (14)에 소개된 반복계산법 및 계산가속기법에 의하여 Lag- range multiplier를 운동 방정식에서 소거한 후 시간 적분을 수행하는 방법을 사용한 다.

• 정보보호학회논문지
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• 제13권3호
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• pp.65-70
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• 2003

본 논문에서는 side-channel 공격법 중 SPA(Simple Power Analysis)에 견디면서도 효율적인 연산이 가능한 scalar multiplication 방법과 하드웨어 구조를 제시한다. 기존에 제시된 SPA에 견디는 스칼라 곱셈 방법은 연산 속도가 느린 것이 약점이다. 따라서 이를 보안하는 방법에 대한 연구는 중요한 분야이다. 본 논문에서 제시한 타원곡선암호법 전용 하드웨어는 SPA에 견디면서도 동일한 유한체 연산기(multiplier, inverter)를 사용한다는 가정 하에 Coron의 방법 보다 연산 속도가 빠른 스칼라 곱셈 방법과 구조를 제시한다. 논문에서 제시하는 하드웨어는 n비트 키를 사용할 때 연산 속도가 2n·(Inversion cycle)+3(Multiplication cycle)만이 소요된다.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• Journal of Mechanical Science and Technology
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• 제20권1호
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• pp.125-132
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• 2006

To understand fluid dynamic forces acting on a structure subjected to two-phase flow, it is essential to get detailed information about the characteristics of two-phase flow. Stratified steady and unsteady two-phase flows between two parallel plates have been studied to investigate the general characteristics of the flow related to flow-induced vibration. Based on the spectral collocation method, a numerical approach has been developed for the unsteady two-phase flow. The method is validated by comparing numerical result to analytical one given for a simple harmonic two-phase flow. The flow parameters for the steady two-phase flow, such as void fraction and two-phase frictional multiplier, are evaluated. The dynamic characteristics of the unsteady two-phase flow, including the void fraction effect on the complex unsteady pressure, are illustrated.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.49-52
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• 2003

Two types of ozone monitors using UV absorption method were tried in consideration of cost of the monitor and precision in measuring. The high concentration ozone monitor for high concentration real time ozone monitoring from ozone generator was composed of a low pressure mercury lamp as UV source, a photo multiplier tube as UV detector and signal processing unit for the most part. This structure could be very useful for low price high concentration ozone monitor due to simple system structure and fairly good monitoring characteristics. The developed system showed good linear output characteristics to ozone in the measuring concentration range of 0.05 and 2 wt.%. For accuracy ambient ozone monitoring in ambient in ppm level, the system composed of a high power pulsed xenon lamp as UV source, an optical spectrometer with a high sensitivity linear CCD array as UV detector and signal processing unit in brief speaking was proposed our study for the first time in the world. The developed system showed good linearity and sensitivity in relative low measuring range between 10ppm and 10,000ppm, and showed some feasibility of high resolution ozone monitor using CCD array as photodetector.

• 대한기계학회논문집A
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• 제29권12권
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• pp.1629-1637
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• 2005

Optimum sensitivity analysis (OSA) is the process to find the sensitivity of optimum solution with respect to the parameter in the optimization problem. The prevalent OSA methods calculate the optimum sensitivity as a post-processing. In this research, a simple technique is proposed to obtain optimum sensitivity as a result of the original optimization problem, provided that the optimum sensitivity of objective function is required. The parameters are considered as additional design variables in the original optimization problem. And then, it is endowed with equality constraints to penalize the additional variables. When the optimization problem is solved, the optimum sensitivity of objective function is simultaneously obtained as Lagrange multiplier. Several mathematical and engineering examples are solved to show the applicability and efficiency of the method compared to other OSA ones.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.121-124
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• 2004

In this paper, Simple and inexpensive analog maximum power point tracker (MPPT) algorithm for photovoltaic power system and low power system of doesn't use digital signal processor (DSP). The control circuit is composed such that the actual current and voltage are sensed directly from the PV array. These two signals are then multiplied by a single-chip multiplier. The multiplier output go through different time constants genesis pulse width modulated to switch. Finally those were verified through simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• 대한기계학회논문집
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• 제17권10호
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• pp.2457-2466
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• 1993

A simple method is presented for determining transient responses of locally nonlinear structures using substructure eigenproperties and Lagrange multiplier technique. Although the method is based upon the mode synthesis formulation procedure, the equations of the combined whole structure are not constructed compared with the conventional methods. Lagrange multi-pliers are used to enforce the conditions of geometric compatibility between the substructure interfaces and they are treated as external forces on each substructure itself. Substructure eigenvalue problem is defined with the substructure interface free of fixed. The transient analysis is based upon the recurrence discrete-time state equations and offers the simplicity of the Euler integration method without requiring small time increment and iterative solution procedure. Numerical examples reveal that the method is very accurated and efficient in calculating transient responses compared with the direct numerical integration method.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.