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http://dx.doi.org/10.13089/JKIISC.2003.13.3.65

A Scalar Multiplication Method and its Hardware with resistance to SPA(Simple Power Analysis)  

윤중철 (고려대학교 정보보호대학원)
정석원 (고려대학교 정보보호대학원)
임종인 (고려대학교 정보보호대학원)
Abstract
In this paper, we propose a scalar multiplication method and its hardware architecture which is resistant to SPA while its computation speed is faster than Colon's. There were SPA-resistant scalar multiplication method which has performance problem. Due to this reason, the research about an efficient SPA-resistant scalar multiplication is one of important topics. The proposed architecture resists to SPA and is faster than Colon's method under the assumption that Colon's and the proposed method use same fmite field arithmetic units(multiplier and inverter). With n-bit scalar multiple, the computation cycle of the proposed is 2n·(Inversion cycle)+3(Aultiplication cycle).
Keywords
SPA;
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