• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.49-57
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• 2002

Including RF Package inductance, substrate coupling through conductive silicon(Si)-substrate is modeled and quantitatively characterized. 2-port substrate coupling model is extended for the characterization of multi-port substrate coupling between digital circuit block and analog/RF circuit block. Furthermore, scalable parameter extraction model is developed. Multi-port substrate coupling can be investigated by linearly superposing a frequency-dependent 2-port substrate coupling model using scalable parameters. In addition, Substrate coupling including RF package inductance effect is quantitatively investigated. It is shown that package effect increases substrate coupling and shifts a characteristic frequencies(i.e., poles) to the higher frequency range. The proposed methodology can be efficiently used to the mixed-signal circuit performance verification.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.141-141
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• 2010

The effect of thermal anneal on the characteristics of structural properties and the enhancement of luminescence and photovoltaic (PV) characteristics of silicon-rich silicon-nitride films were investigated. By using an ultra high vacuum ion beam sputtering deposition, B-doped silicon-rich silicon-nitride (SRSN) thin films, with excess silicon content of 15 at. %, on P-doped (n-type) Si substrate was fabricated, sputtering a highly B doped Si wafer with a BN chip by N plasma. In order to examine the influence of thermal anneal, films were then annealed at different temperature up to $1100^{\circ}C$ under $N_2$ environment. Raman, X-ray diffraction, and X-ray photoemission spectroscopy did not show any reliable evidence of amorphous or crystalline Si clusters allowing us concluding that nearly no Si nano-cluster could be formed through the precipitation of excess Si from SRSN matrix during thermal anneal. Instead, results of Fourier transform infrared and X-ray photoemission spectroscopy clearly indicated that defective, amorphous Si-N matrix of films was changed to be well-ordered thanks to high temperature anneal. The measurement of spectral ellipsometry in UV-visible range was carried out and we found that the optical absorption edge of film was shifted to higher energy as the anneal temperature increased as the results of thermal anneal induced formation of $Si_3N_4$-like matrix. These are consistent with the observation that higher visible photoluminescence, which is likely due to the presence of Si-N bonds, from anneals at higher temperature. Based on these films, PV cells were fabricated by the formation of front/back metal electrodes. For all cells, typical I-V characteristic of p-n diode junction was observed. We also tried to measure PV properties using a solar-simulator and confirmed successful operation of PV devices. Carrier transport mechanism depending on anneal temperature and the implication of PV cells based on SRSN films were also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• Journal of Applied Reliability
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• v.16 no.1
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• Journal of the Korean Ceramic Society
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• v.28 no.11
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• pp.859-864
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• 1991

High quality lead titanate thin films were fabricated by spin coating on a silicon substrate. The resulting dried gel layers were uniform in thickness through 2$\times$2 $\textrm{cm}^2$ area, and polycrystalline perovskite structures developed almost crack free with a heat treatment above 50$0^{\circ}C$ in films with thickness above 360 nm. Metastable pyrochlore structures were observed in films with thickness of 160 nm when heat treated at 500 and $600^{\circ}C$, but these structure did not appear in films with thickness of 360 nm. The thickness dependence in crystal structure of films was studied. by varying the substrate condition and analyzing the interface between the film and substrate. In native oxide films on silicon stbstrates, amorphous dried gel layers were heterogeneously nucleated. Metastable cubic pyrochlore structure could be crystallized in amorphous native oxide.

• Journal of Integrative Natural Science
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• v.5 no.4
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• pp.211-215
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• 2012

Single-crystalline silicon nanowire arrays (SiNWAs) using electroless metal-assisted etchings of p-type silicon were successfully fabricated. Ag nanoparticle deposition on silicon wafers in HF solution acted as a localized micro-electrochemical redox reaction process in which both anodic and cathodic process took place simultaneously at the silicon surface to give SiNWAs. The growth effect of SiNWs was investigated by changing of etching times. The morphologies of SiNWAs were obtained by SEM observation. Well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. Optical characteristics of SiNWs were measured by FT-IR spectroscopy and indicated that the surface of SiNWs are terminated with hydrogen. The thicknesses and lengths of SiNWs are typically 150-250 nm and 2 to 5 microns, respectively.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.2
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• pp.70-77
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• 2007

The application of focused ion beam(FIB) technology has been broadened in the fabrication of nanoscale regime. The extended application of FIB is dependent on complicated reciprocal relation of operating parameters. It is necessary for successful and efficient modifications on the surface of silicon substrate. The primary effect by Gaussian beam intensity is significantly shown from various aperture size, accelerating voltage, and beam current. Also, the secondary effect of other process factors - dwell time, pixel interval, scan mode, and pattern size has affected to etching results. For the process analysis, influence of the secondary factors on FIB micromilling process is examined with respect to sputtering depth during the milling process in silicon material. The results are analyzed by the ratio of signal to noise obtained using design of experiment in each parameter.

• Transactions on Electrical and Electronic Materials
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• v.8 no.4
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• pp.170-173
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated the organic field-effect transistor based a copper phthalocyanine (CuPc) as an active layer on the silicon substrate. The CuPc FET device was made a topcontact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in CuPc FET and we calculated the effective mobility with each device. Also, we observed the AFM images with different substrate temperature.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.40-42
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• 2011

An organic field-effect transistor (OFET) was fabricated using a copper phthalocyanine (CuPc) as the active layer on the silicon substrate. The CuPc FET device was configured as a top-contact type. The substrate temperature was room temperature. The CuPc thickness was 40 nm, and the channel length and channel width were 100 ${\mu}m$ 3 mm, respectively. Typical current-voltage (I-V) characteristics of the CuPc FET were observed and subsequently compared to the UV/ozone treatment on substrate surface.