Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Silicon Substrate Coupling Modeling and Analysis including RF Package Inductance

RF 패키지 인덕턴스가 실리콘 기판 커플링에 미치는 영향 모델링 및 해석

  • Jin, U-Jin (Dept. of Electronic computer Engineering, Hanyang University) ;
  • Eo, Yeong-Seon (Dept. of Electronic computer Engineering, Hanyang University) ;
  • Sim, Jong-Jin (Dept. of Electronic computer Engineering, Hanyang University)
  • 진우진 (한양대학교 전자컴퓨터공학부) ;
  • 어영선 (한양대학교 전자컴퓨터공학부) ;
  • 심종진 (한양대학교 전자컴퓨터공학부)
  • Published : 2002.01.01
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Abstract

Including RF Package inductance, substrate coupling through conductive silicon(Si)-substrate is modeled and quantitatively characterized. 2-port substrate coupling model is extended for the characterization of multi-port substrate coupling between digital circuit block and analog/RF circuit block. Furthermore, scalable parameter extraction model is developed. Multi-port substrate coupling can be investigated by linearly superposing a frequency-dependent 2-port substrate coupling model using scalable parameters. In addition, Substrate coupling including RF package inductance effect is quantitatively investigated. It is shown that package effect increases substrate coupling and shifts a characteristic frequencies(i.e., poles) to the higher frequency range. The proposed methodology can be efficiently used to the mixed-signal circuit performance verification.

이 논문에서는 패키지 인덕턴스를 고려한 다중 단자에서의 전도성 실리콘 기판에서의 커플링을 모델링하고 정량적으로 특성화한다. 이것을 위해 2단자 커플링 모델로부터 추출할 수 있는 모델 파라미터를 일반적인 구조에 적용할 수 있도록 개선하였다. 그리고 다중 단자의 노이즈 소스에 의한 기판 커플링 특성을 위해 기판의 주파수 의존적인 특성을 정확히 반영하는 2단자 기판 커플링 모델을 선형적으로 결합함으로써 일반적인 구조에 적용될 수 있도록 확장하였다. 또한 패키지 인덕턴스는 시스템의 특성 주파수를 높은 주파수 영역으로 이동시킴으로써 결과적으로 기판 커플링을 증가시키므로 정확한 분석이 요구된다. 따라서 기판 커플링 모델에 패키지 인덕턴스 성분을 추가하고 이를 정량적으로 분석함으로써 설계 초기 단계에서 패키지의 영향과 기판 커플링의 영향을 동시에 고려한 회로 성능 분석이 가능하도록 하였다. 그러므로 이 논문에서 제안한 방법은 복잡한 혼성 신호 회로의 성능 분석에 매우 유용하게 이용될 수 있다.

Keywords

References

  1. L. E. Larson, 'Integrated circuit technology options for RFIC's-present status and future directions,' IEEE J. Solid-State Circuits, Vol. 33, No. 3, pp. 387-399, Mar. 1998 https://doi.org/10.1109/4.661204
  2. L. E. Larson, 'Device and technology requirements for next generation communications systems,' IEDM Technical Digest, Electron Devices Meeting, 2000, pp. 737-740 https://doi.org/10.1109/IEDM.2000.904423
  3. C. Kim, J. Park, H.Yu, and H. Cho, 'Gate layout and bonding pad structure of a RF nMOSFET for low noise performance,' IEEE Electron Device Lett., Vol. 21, No. 12, pp. 607-609, Dec. 2000 https://doi.org/10.1109/55.887481
  4. R. C. Frye, 'Integration and electrical isolation in CMOS mixed-signal wireless chips,' Proc. IEEE, Vol. 89, No. 4, pp. 444-455, Apr. 2001 https://doi.org/10.1109/5.920577
  5. A. Matsuzawa, 'High quality analog CMOS and mixed signal LSI design,' Quality Electronic Design, 2001 International Symposium on, 2001, pp. 97-104 https://doi.org/10.1109/ISQED.2001.915212
  6. The international technology roadmap for semiconductors, SIA Report, 1999
  7. M. Felder and J. Ganger, 'Analysis of groundbounce induced substrate noise coupling in a low resistive bulk epitaxial process : design strategies to minimize noise effects on a mixed-signal chip,' IEEE Trans. Circuits Syst. II, Vol. 46, No. 11, pp. 1427-1436, Nov. 2000 https://doi.org/10.1109/82.803483
  8. K. B. Unchwaniwala and M. F. Caggiano, 'Effects of integrated circuit packaging on performance of a LNA in a mixed-signal circuit environment,' Mixed-Signal Design, 2001, SSMSD, 2001 South west Symposium on, 2001, pp. 76-79 https://doi.org/10.1109/SSMSD.2001.914941
  9. K. M. Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, 'Measurement of digital noise in mixed-signal integrated circuits,' IEEE J. Solid-State Circuits, Vol. 30, No. 2, pp. 87-92, Feb. 1995 https://doi.org/10.1109/4.341734
  10. M. Ingels and M. S. J. Steyaert, 'Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's,' IEEE J. Solid-State Circuits, Vol. 32, No. 7, pp. 1136-1141, Jul. 1997 https://doi.org/10.1109/4.597306
  11. M. Nagata, J. Nagai, T. Morie, and A. Iwata, 'Measurements and analyses of substrate noise waveform in mixed-signal IC environment,' IEEE Trans. Computer-Aided Design, Vol. 19, No. 6, pp. 671-678, Jun, 2000 https://doi.org/10.1109/43.848088
  12. M. V. Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. G. E. Engels, and I. Bolsens, 'Analysis and experimental verification of digital substrate noise generation for epi-type substrates,' IEEE J. Solid-State Circuits, Vol. 35, No. 7, pp. 1002-1008, Jul. 2000 https://doi.org/10.1109/4.848209
  13. A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, 'A scalable substrate noise coupling model for design of mixed-signal IC's,' IEEE J. Solid-State Circuits, Vol. 35, No. 6, pp. 895-904, Jun. 2000 https://doi.org/10.1109/4.845193
  14. M. Pfost and H. M. Rein, 'Modeling and measurement for substrate coupling in SiBipolar IC's up to 40GHz,' IEEE J. Solid-State Circuits, Vol. 33, No. 4, pp. 582-591, Apr. 1998 https://doi.org/10.1109/4.663563
  15. N. Masoumi, S. S-. Naeini, M. I. Elmasry, and Y. L. Chow, 'A semi-analytical quasi-static approach for substrate coupling modeling in VLSI circuits,' The 12th Intemational conference on Microelectronics, 2000, pp. 157-160 https://doi.org/10.1109/ICM.2000.916435
  16. W. Jin, Y. Eo, J. Shim, W. R. Eisenstadt, M. Park, and H. Yu, 'Silicon substrate coupling noise modeling, analysis, and experimental verification for mixed signal integrated circuit design,' International Microwave Symposium Digest, 2001, pp. 1727-1730 https://doi.org/10.1109/MWSYM.2001.967239
  17. J. Huchzermeier, 'Comparison of electrical and thermal parameters of widebus SMD SSOP, TSSOP, TVSOP, and LFBGA packages,' Application report, Texas Instruments, 1999