• Journal of the Korean institute of surface engineering
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• v.47 no.1
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• pp.20-24
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• 2014

Joule heat is generated by applying an electric filed to a conductive layer located beneath or above the amorphous silicon film, and is used to raise the temperature of the silicon film to crystallization temperature. An electric field was applied to an indium tin oxide (ITO) conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced within the range of a millisecond. To investigate the kinetics of Joule-heating induced crystallization (JIC) solid phase crystallization was conducted using amorphous silicon films deposited by plasma enhanced chemical vapor deposition and using tube furnace in nitrogen ambient. Microscopic and macroscopic uniformity of crystallinity of JIC poly-Si was measured to have better uniformity compared to that of poly-Si produced by other methods such as metal induced crystallization and Excimer laser crystallization.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.103-105
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• 2015

Effect of silicon doping into ZnSnO systems was investigated using solution process. Addition of silicon was used to suppress oxygen vacancy generation. The transfer characteristics of the device showed threshold voltage shift toward the positive direction with increasing Si content due to the high binding energy of silicon atoms with oxygen. As a result, the carrier concentration was decreased with increasing Si content.

• Journal of Integrative Natural Science
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• v.6 no.3
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• pp.170-175
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• 2013

Silicon nanowires were detached and obtained from silicon nanowire arrays on silicon substrate using a ultrasono-method. Silicon nanowire arrays on silicon substrate were prepared with an electroless metal assisted etching of p-type silicon. The etching solution was an aqueous HF solution containing silver nitrate. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. After sonication of silicon nanowire array, an individual silicon nanowire was confirmed by FESEM. Optical characteristics of SiNWs were measured by FT-IR spectroscopy. The surface of SiNWs are terminated with hydrogen.

• Journal of the Korean Ceramic Society
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• v.53 no.3
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• pp.349-353
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• 2016

We prepared a number of reaction-bonded silicon carbides (RBSCs) made from various mixing ratios of raw SiC particles, and investigated their microstructure and etch characteristics by Reactive Ion Etch (RIE). Increasing the amount of $9.5{\mu}m$-SiC particles results in a microstructure with relatively coarser Si regions. On the other hand, increasing that of $2.6{\mu}m$-SiC particles produces much finer Si regions. The addition of more than 50 wt% of $2.6{\mu}m$-SiC particles, however, causes the microstructure to become partially coarse. We also evaluated their etching behaviors in terms of surface roughness (Ra), density and weight changes, and microstructure development by employing Confocal Laser Scanning Microscope (CLSM) and Scanning Electron Microscope (SEM) techniques. During the etching process of the prepared samples, we confirmed that the residual Si region was rapidly removed and formed pits isolating SiC particles as islands. This leads to more intensified ion field on the SiC islands, and causes physical corrosion on them. Increased addition of $2.6{\mu}m$-SiC particles produces finer residual Si region, and thus decreases the surface roughness (Ra.) as well as causing weight loss after etching process by following the above etching mechanism.

• 전기의세계
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• v.22 no.2
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• pp.11-18
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• 1973

This paper reports some results of Si and SiO$_{2}$ films obtained from the expitaxial growth by hydrogen reduction of SiCI$_{4}$ with a hydrogen and carbon dioxide mixture in an epitaxial-deposition chamber. The deposited Si and SiO$_{2}$ are studied by observing the process parameters affecting the rate of deposition, and the quantitative properties at the interface of Si and SiO$_{2}$ are also considered briefly according to the results of the optical absorption and the voltage-current characteristic of MOS etc. using step etching procedure for oxide films.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.67-68
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• 2000

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

• Resources Recycling
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• v.31 no.6
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• pp.60-65
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• 2022

This study presents the carburization process for recycling sludge, which was formed during silicon wafer machining. The sludge used in the carburization process is a mixture of silicon and silicon carbide (SiC) with iron as an impurity, which originates from the machine. Additionally, the sludge contains cutting oil, a fluid with high viscosity. Therefore, the sludge was dried before carburization to remove organic matter. The dried sludge was washed by acid cleaning to remove the iron impurity and subsequently carburized by heat treatment under vacuum to form the SiC powder. The ratio of silicon to SiC in the sludge was varied depending on the sources and thus carbon content was adjusted by the ratio. With increasing SiC content, the carbon content required for SiC formation increased. It was demonstrated that substoichiometric SiC_x (x<1) was easily formed when the carbon content was insufficient. Therefore, excess carbon is required to obtain a pure SiC phase. Moreover, size reduction by high-energy milling had a beneficial effect on the suppression of SiC_x, forming the pure SiC phase.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.183-189
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• 1992

The characteristics of N/O(SiOz/SisN4) film on WSi2 are compared with storage node Poly-Si. Leakage current and breakdown voltage are improved and storage capacitance is decreased. The oxidation rate of WSiz is more rapid than polycrystalline silicon. Thus the thick bottom oxide on the WSiz causes to the decrease of capacitance. The out diffusion of dopant impurity in polycrystalline silicon through the silicide leads to the formation of a depletion region in the polycrystalline silicon and the decrease of depletion capacitance. That results in the decrease of the overall storage capacitance.

• Journal of the Korean institute of surface engineering
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• v.35 no.4
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• pp.211-217
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• 2002

Ti-Si-N films were deposited onto WC-Co substrate by a RF-PECVD technique. The deposition behaviors of Ti-Si-N films were investigated by varying the deposition temperature, RF power, and reaction gas ratio (Mx). Ti-Si-N films deposited at 500, 180W, and Mx 60% had a maximum hardness value of 38GPa. The microstructure of films with a maximum hardness was revealed to be a nanocomposite of TiN crystallites penetrated by amorphous silicon nitride phase by HRTEM analyses. The microstructure of maximum hardness with Si content (10 at.%) was revealed to be a nanocomposite of TiN crystallites penetrated by amorphous silicon nitride phase, but to have partly aligned structure of TiN and some inhomogeniety in distribution. and At above 10 at.% Si content, TiN crystallite became finer and more isotropic also thickness of amorphous silicon nitride phase increased at microstructure.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.