• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.243-246
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• 1999

We studied the MOSFET characteristics and the hot-carrier reliability with the sidewall spacer composition and the post gate oxidation thickness in 0.20${\mu}{\textrm}{m}$ gate length transistor. The MOSFET with NO(Nitride＋Oxide) sidewall spacer exhibits the large degradation of hot-carrier lifetime because there is no buffering oxide against nitride stress. When the post gate oxidation is skipped, the hot-carrier lifetime is improved, but GIDL (Gate Induced Drain Leakage) current is also increased.

• 한국진공학회지
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• 제13권1호
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• pp.34-38
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• 2004

핫엠보싱 기술을 이용하여 고분자 광도파로를 제작하기 위해서는 핫엠보싱 마스터가 필수적이며, 본 연구에서는 deep-RIE 공정에 의해 실리콘 마스터를 제작하였다. 광도파로의 광손실과 직접 연관이 있는 실리콘 마스터의 측면 거칠기를 최소화하기 위해 deep-RIE 공정 수행 후, 온도 $1050^{\circ}C$에서 $H_2/O_2$ 분위기하에 산화층을 각각 400$\AA$, 1000$\AA$, 3000$\AA$, 4500$\AA$, 5600$\AA$ 및 6200$\AA$ 두께로 형성하였으며, 곧바로 $NH_4$F:HF=6:1 BOE를 사용하여 산화층을 제거하였다. 제작된 마스터의 측면 거칠기를 SPM-AFM을 이용하여 측정하였으며, 측면 거칠기가 scallop 부분의 경우, 산화층 형성과 제거 후, 12nm (RMS)에서 최소 약 6nm (RMS)로 개선되었으며, vertical striation부분은 162nm (RMS)에서 최소 39m (RMS)로 개선됨을 확인하였다.

• 한국전자통신학회논문지
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• 제7권4호
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• pp.833-837
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• 2012

SC1(Standard Cleaning) 시간을 줄여 STI 측벽에서의 실리콘 손실 및 과도절개를 최소화하여 DRAM에서의 데이터 유지시간을 증가시키는 방법을 제안한다. SC1 시간 최적화를 통해 STI 상층 모서리부에서의 기생 전기장을 약화시킴으로서 Inverse Narrow Width 효과를 감소시키면 셀 트랜지스터의 Subthreshold 누설의 증가없이 채널 도핑농도가 감소하게 된다. 이것은 셀 접합에서 P-Well간 공핍 영역에서의 전기장을 최소화하여 일드나 데이터 유지시간의 증가를 보여 주었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.288-288
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• 2012

The oxidation characteristics of tungsten line pattern during the carbon-based mask layer removal process using oxygen plasmas and the reduction characteristics of the WOx layer formed on the tungsten line surface using hydrogen plasmas have been investigated for sub-50 nm patterning processes. The surface oxidation of tungsten line during the mask layer removal process could be minimized by using a low temperature ($300^{\circ}K$) plasma processing instead of a high temperature plasma processing for the removal of the carbon-based material. Using this technique, the thickness of WOx on the tungsten line could be decreased to 25% of WOx formed by the high temperature processing. The WOx layer could be also completely removed at the low temperature of $300^{\circ}K$ using a hydrogen plasma by supplying bias power to the tungsten substrate to provide an activation energy for the reduction. When this oxidation and reduction technique was applied to actual 40 nm-CD device processing, the complete removal of WOx formed on the sidewall of tungsten line could be observed.

• 전자공학회논문지A
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• 제31A권12호
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• 한국표면공학회지
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• 제31권5호
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• pp.237-244
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• 1998

In this stydy, submicron shallow trenches applied to STI(shallow tench isolation) were etched using inductively coupled $CI_2$/HBr and $CI_2/N_2$plasmas and the physical and electrical defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. Using high resolution electron microscopy(HRTEM), Physical defects were investigated on the silicon trench surfaces etched in both 90%$CI_2$/ 10%$N_2$ and 50%$CI_2$/50%HBr. Among the areas in the tench such as trench bottom, bottom edge, and sidewall, the most dense defects were found near the trench bottom edge, and the least dense defects were found near the trench bottom edge, and least dense defects compared to that etched with ment as well as hydrogen permeation. Thermal oxidation of 200$\AA$ atthe temperature up to $1100^{\circ}C$apprars not to remove the defects formed on the etched silicon trenches for both of the etch conditions. To remove the physicall defects, an annealing treatment at the temperature high than $1000^{\circ}C$ in N for30minutes was required. Electrical defects measured using a capacitance-voltage technique showed the reduction of the defects with increasing annealing temperature, and the trends were similar to the results on the physical defects obtained using transmission electron microscopy.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.254-259
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• 2007

In this report, several fabrication techniques for the formation of various nanochannels (with $SiO_2$, Si, or Quartz) are introduced. Moreover, simple fabrication technique for generating $SiO_2$ nanochannels without nanolithography is presented. By using different nanochannels, the degree of stretching DNA molecule will be evaluated. Finally, we introduce a nanometer scale fluidic channel with electrodes on the sidewall of it, to detect and analyze single DNA molecule. The cross sectional shape of the nanotrench is V-groove, which was implemented by thermal oxidation. Electrodes were deposited through both sidewalls of nanotrench and the sealing of channel was done by covering thin poly-dimethiysiloxane (PDMS) polymer sheet.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• 한국통신학회논문지
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• 제15권3호
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• pp.252-259
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• 1990

本 論文은 기존 LOCOS工程의 張點을 모두 겸비한 側面璧 SWAMI 技術에 대한 새로운 構造를 提示한다. 새로운 SWAMI공정은 순수 窒化膜 壓力과 體積 膨腸에 기인한 壓力을 크게 줄이기 위해서 側面璧 주위에 얇은 질화막과 反應性이온 飾刻으로 기울어진 실리콘 측면벽을 結合시켰따. 製作된 結果에 의하면, 缺陷이 없는 완전히 새부리 모양이 形成되지 않는 局地的 酸化 공정은 기울어진 面의 異方性 산화 隔離에 의해 實現시킬 수 있었다. 추가적인 마스크 段階는 要求되지 않는다. 이 工程에서 PN 다이오드의 漏泄電流는 기존 LOCOS 공정 보다 減少되었다. 한편 가장자리 部位는 漏泄電流 密度에서 평편한 接合 부위 보다 높게 分析되었다.

• 전자공학회논문지
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• 제51권3호
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• pp.177-184
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• 2014

화학기상증착의 텅스텐 실리사이드 듀얼 폴리 게이트 구조에서 플로린이 게이트 산화막에 미치는 영향을 전기적 물리적 측정 방법을 사용하여 연구하였다. 플로린을 많이 함유한 텅스텐 실리사이드 NMOS 트랜지스터에서 채널길이가 감소함에 따라 게이트 산화막 두께는 감소하여 트랜지스터의 롤업(roll-off) 특성이 심화된다. 이는 게이트 재 산화막 열처리 공정에 의해 수직방향으로의 플로린 확산과 더불어 수평방향인 게이트 측면 산화막으로의 플로린 확산에 기인한다. 채널길이가 짧아질수록 플로린의 측면방향 확산거리가 작아져 수평방향 플로린 확산이 증가하고 그 결과 게이트 산화막의 두께는 감소하게 된다. 반면에 PMOS 트랜지스터에서는 P형 폴리를 만들기 위한 높은 농도의 붕소가 플로린의 게이트 산화막으로의 확산을 억제하여 채널길이에 따른 산화막 두께 변화 특성이 보이지 않는다.