• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.243-246
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• 1999

We studied the MOSFET characteristics and the hot-carrier reliability with the sidewall spacer composition and the post gate oxidation thickness in 0.20${\mu}{\textrm}{m}$ gate length transistor. The MOSFET with NO(Nitride＋Oxide) sidewall spacer exhibits the large degradation of hot-carrier lifetime because there is no buffering oxide against nitride stress. When the post gate oxidation is skipped, the hot-carrier lifetime is improved, but GIDL (Gate Induced Drain Leakage) current is also increased.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.34-38
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• 2004

Hot embossing master is indispensable for the fabrication of polymeric optical waveguides using hot embossing technology. Sidewall roughness of silicon master is directly related to optical loss of optical waveguides In this paper, a silicon master was fabricated by using a deep-RIE process. Additionally, thermal oxidation followed by oxide removal was carried out to minimize etched Si sidewall roughness. Thermal oxidation and oxide removal were performed with $H_2O_2$ atmosphere at $1050^{\circ}C$ and $NH_4$F:HF=6:l BOE, respectively, for the oxide thickness of 400$\AA$, 1000$\AA$, 3000$\AA$, 4500$\AA$, 5600$\AA$ and 6200$\AA$. The sidewall roughness was characterized by SEM and SPM-AFH measurements. We found that the roughness was improved from 12nm (RMS) to 6nm (RMS) for the scalloped sidewall and from 162nm (RMS) to 39nm (RMS) for the vertical striation sidewall, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.833-837
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• 2012

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.288-288
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• 2012

The oxidation characteristics of tungsten line pattern during the carbon-based mask layer removal process using oxygen plasmas and the reduction characteristics of the WOx layer formed on the tungsten line surface using hydrogen plasmas have been investigated for sub-50 nm patterning processes. The surface oxidation of tungsten line during the mask layer removal process could be minimized by using a low temperature ($300^{\circ}K$) plasma processing instead of a high temperature plasma processing for the removal of the carbon-based material. Using this technique, the thickness of WOx on the tungsten line could be decreased to 25% of WOx formed by the high temperature processing. The WOx layer could be also completely removed at the low temperature of $300^{\circ}K$ using a hydrogen plasma by supplying bias power to the tungsten substrate to provide an activation energy for the reduction. When this oxidation and reduction technique was applied to actual 40 nm-CD device processing, the complete removal of WOx formed on the sidewall of tungsten line could be observed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• Journal of the Korean institute of surface engineering
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• v.31 no.5
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• pp.237-244
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• 1998

In this stydy, submicron shallow trenches applied to STI(shallow tench isolation) were etched using inductively coupled $CI_2$/HBr and $CI_2/N_2$plasmas and the physical and electrical defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. Using high resolution electron microscopy(HRTEM), Physical defects were investigated on the silicon trench surfaces etched in both 90%$CI_2$/ 10%$N_2$ and 50%$CI_2$/50%HBr. Among the areas in the tench such as trench bottom, bottom edge, and sidewall, the most dense defects were found near the trench bottom edge, and the least dense defects were found near the trench bottom edge, and least dense defects compared to that etched with ment as well as hydrogen permeation. Thermal oxidation of 200$\AA$ atthe temperature up to $1100^{\circ}C$apprars not to remove the defects formed on the etched silicon trenches for both of the etch conditions. To remove the physicall defects, an annealing treatment at the temperature high than $1000^{\circ}C$ in N for30minutes was required. Electrical defects measured using a capacitance-voltage technique showed the reduction of the defects with increasing annealing temperature, and the trends were similar to the results on the physical defects obtained using transmission electron microscopy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.254-259
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• 2007

In this report, several fabrication techniques for the formation of various nanochannels (with $SiO_2$, Si, or Quartz) are introduced. Moreover, simple fabrication technique for generating $SiO_2$ nanochannels without nanolithography is presented. By using different nanochannels, the degree of stretching DNA molecule will be evaluated. Finally, we introduce a nanometer scale fluidic channel with electrodes on the sidewall of it, to detect and analyze single DNA molecule. The cross sectional shape of the nanotrench is V-groove, which was implemented by thermal oxidation. Electrodes were deposited through both sidewalls of nanotrench and the sealing of channel was done by covering thin poly-dimethiysiloxane (PDMS) polymer sheet.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.252-259
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• 1990

This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.177-184
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• 2014

In chemical vapor deposition(CVD) tungsten silicide(WSix) dual poly gate(DPG) scheme, we observed the fluorine effects on gate oxide using the electrical and physical measurements. It is found that in fluorine-rich WSix NMOS transistors, the gate thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In PMOS transistors, it is observed that boron of background dopoing in $p^+$ poly retards fluorine diffusion into the gate oxide. Thus, it is suppressed the fluorine effects on gate oxide thickness with the channel length dependency.