• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• 전자공학회논문지A
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• 제29A권2호
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• pp.68-76
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• 1992

Concurrent Junction process (simultaneous formation of a silicide and a junction on the implanted substrate) by Rapid Thermal Annealig has been investigated. Electrical and material properties of CoSi$_2$ films were analyzed with Alpha Step, 4-point probe, X-ray diffraction(XRD) and Scanning Electron Microscope(SEM). And CoSi$_2$ junctions were examined with Spreading Resistance probe in order to see the redistribution of electrically activated dopants and determined the junction depth. Two step annealing process, which was 80$0^{\circ}C$ for 30sec and 100$0^{\circ}C$ for 30sec in NS12T ambient was employed to form CoSi$_2$ and shallow junctions. Resistivity of CoSi$_2$ was turned out to be 11-15${\mu}$cm and shallow junctions less than 0.1$\mu$m were successfully formed by the process. It was found that the dopant concentration at CoSi$_2$/Si interface increased as decreasing the thickness of Co films in case of $p^{+}/n$ and $n^{+}/p$ junctions while the junction depth decreased as increasing CoSiS12T thickness in case of $p^{+}/n$ junction.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권6호
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• pp.300-304
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• 2004

We have proposed the junction termination design employing shallow trench filled with silicon dioxide and field limiting ring (FLR). We have designed trenches between P+ FLRs to decrease the junction termination radius without sacrificing the breakdown voltage characteristics. We have successfully fabricated and measured improved breakdown voltage characteristics of the Proposed device for 1200 V-class applications. The junction termination radius of the proposed device has decreased by 15%-21% compared with that of the conventional FLR at the identical breakdown voltage. The junction termination area of the proposed device has decreased by 37.5% compared with that of the conventional FLR. The breakdown voltage of the proposed device employing 7 trenches was 1156 V, which was 80% of the ideal parallel-plane .junction breakdown voltage.

• 전자공학회논문지D
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• 제35D권5호
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• pp.87-92
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• 1998

Ultr shallow p$^{+}$-n junction with Co/Ti bilayer silicidde contact was formed by ion implantation of BF$_{2}$ [energy : (30, 50)keV, dose:($5{\times}10^{14}$, $5{\times}10^{15}$/$\textrm{cm}^2$] onto the n-well Si(100) region and by RTA-silicidation and post annealing of the evaporated Co(120.angs., 170.angs.)/Ti(40~50.angs.) double layer. The sheet resistance of the silicided p$^{+}$ region of the p$^{+}$-n junction formed by BF2 implantation with energy of 30keV and dose of $5{\times}10^{15}$/$\textrm{cm}^2$ and Co/Ti thickness of $120{\AA}$/(40~$50{\AA}$) was about $8{\Omega}$/${\box}$. The junction depth including silicide thickness of about $500{\AA}$ was 0.14${\mu}$. The fabricated p$^{+}$ -n ultra shallow junction depth including silicide thickness of about $500{\AA}$ was 0.14${\mu}$. The fabricated p$^{+}$-n ultra shallow junction with Co/Ti bilayer silicide contact did not show any agglomeration or variation of sheet resistance value after post annealing at $850^{\circ}C$ for 30 minutes. The boron concentration at the epitaxial CoSi$_{2}$/Si interface of the fabricated junction was about 6*10$6{\times}10^{19}$ / $\textrm{cm}^2$./TEX>.

• 전자공학회논문지A
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• 제31A권12호
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.29-32
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• 2002

This paper describes a novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension(SDE)region. A new ultra-shallow junction formation technology. Which is based on damage-free process for rcplacing of low energy ion implantation, is realized using ultra-high vacuum chemical vapor deposition(UHVCVD) and excimer laser annealing(ELA).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.171-171
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• 2000

차세대 반도체 제조에서 Design rule 이 점점 더 shrink 됨에 따라 shallow junction 분석의 중요성이 강조되고 있다. 이러한 shallow junction에 대한 분석방법중의 하나인 SIMS 분석에 있어서 depth resolution을 향상시키는 것이 중요하며, 일차이온의 에너지를 낮추어 줌으로써 이러한 효과를 달성할 수 있다. 그러나 최근의 연구에 따르면 O2+를 이용한 low energy SIMS 분석 시에 non-zero incidence angle로 분석할 경우 surface roughness가 발생한다는 사실이 보고되었으며, surface roughness를 줄이고 분석 초기의 transient region을 줄이기 위한 방법으로 oxygen flooding을 사용하는 경우 특정 각도에서 surface roughness가 여전히 존재할 뿐 아니라 분석 초기영역에서의 sputter rate이 변화하는 문제가 있음이 보고된바 있다. 본 연구에서는 2keV O2+ 일차이온을 이용하여 oxygen flooding 하에서 기존 조건인 60도 incidence로 분석하는 방법의 문제점을 파악하고 incidence angle을 45도로 바꾸어 분석하는 방법을 검토하였다. 그 결과 기존의 분석조건에서는 분석도중 표면부근에서 sputter rate이 변화하고 surface roughness가 증가하는 것을 확인하였고, 그로 인하여 oxygen flooding을 하지 않은 경우와 많은 차이가 발생하는 것을 발견하였다. Incidence angle을 45도로 바꾼 결과 이러한 문제가 해결되는 것을 확인하였으며, 특히 GaAs $\delta$layer 분석을 통하여 이 분석조건이 기존의 분석조건에 비하여 획기적으로 향상되는 것을 확인 할 수 있었다. 또한 여러 가지 shallow junction 분석을 통하여 이 분석방법이 상당히 신뢰성이 있음을 알 수 있었다. 그러나 여전히 oxygen flooding을 하지 않은 경우에 비하여 다소간의 차이가 있는 것이 발견되었는데, 이는 주로 표면에 잔존하는 산화막에 의한 효과와 oxygen flooding에서 보다 더 depth resolution이 좋음으로 인하여 발생하는 것으로 추정되었으며 그 밖에 다른 가능성도 제기되었다. 따라서 이 방법은 표면 산화막이 거의 없는 시료에 대하여 적용한다면 oxygen flooding을 하지 않은 경웨 비하여 transient region이 거의 없고 junction depth를 보다 신뢰성 있게 측정할 수 잇는 장점이 있는 것으로 판단되었다. As, P의 저 에너지이온 주입시료에 대해 이 분석방법을 적용할 경우 C+s 분석법에 비하여 depth resolution을 비교적 쉽게 향상시킬 수 있었고, oxygen follding을 쓰지 않은 경우에 비해서는 검출한도를 약 100배 정도 향상시킬 수 있었다. 그러나 2.5keV Cs+ 분석법에 비하면 아직 depth resolution이 불충분하여 실제로 shallow As 분석에 적용하기에는 다소 문제점이 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.603-606
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• 2005

In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.