• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.525-527
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• 2000

BPMT는 워크플로우 관리 시스템에서 프로세스의 정의 도구이다. BPMT는 워크플로우 시스템의 종속된 도구이기 때문에 워크플로우 시스템에서 요구하는 사항에 대처하기 위한 방안으로 확장성과 재사용성이 필수적이다. 이러한 확장성과 재사용성을 달성하기 위해 본 논문에서는 객체지향적인 개발 방법을 선책하고 BPMT에 적합한 디자인 패턴인 Visitor 패턴과 Serializer 패턴을 사용하였다. Visitor 패턴을 이용하면 새로운 표현 방법을 추가하고자 할 때 새로운 모듈만 추가한다는 점에서 표현의 확장성을 달성할 수 있다. 또한 Serializer를 이용함으로써 저장매체에 독립적인 입출력을 가능케 하고 하나의 인터페이스를 제공함으로써 객체의 확장성을 달성하였다.

• Journal of Astronomy and Space Sciences
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• v.31 no.3
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• pp.235-240
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• 2014

The communications link in a space program is a crucial point for upgrading its performance by handling data between spacecraft bus and payloads, because spacecraft's missions are related to the data handling mechanism using communications ports such as a controlled area network bus (CAN Bus) and a universal asynchronous receiver and transmitter (UART). The NEXTSat-1 has a lot of communications ports for performing science and technology missions. However, the top level system requirements for the NEXTSat-1 are mass and volume limitations. Normally, the communications for units shall be conducted by using point to point link which require more mass and volume to interconnect. Thus, our approach for the novel communications link in the NEXTSat-1 program is to use CAN and serializer and deserializer low voltage differential signal (SerDesLVDS) to meet the system requirements of mass and volume. The CAN Bus and SerDesLVDS were confirmed by using already defined communications link for our missions in the NEXTSat-1 program and the analysis results were reported in this study in view of data flow and size analysis.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.753-758
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• 2009

Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• Journal of Sensor Science and Technology
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• v.19 no.6
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• pp.469-474
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• 2010

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 um CMOS process and the measured total output jitter was less than 0.1 UIpp(unit-interval, peak-to-peak) over 20 kHz to 80 MHz bandwidth. The jitter of the CMU output only was measured as 0.2 ps,rms. The transmitter dissipates less than 200 mW from 1.5 V/2.5 V power supplies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.39-45
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• 2004

This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.