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Design of 1.5MHz Serial ATA Physical Layer  

박상봉 (세명대학교 정보통신과)
신영호 (㈜애트랩)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.2, 2004 , pp. 39-45 More about this Journal
Abstract
This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.
Keywords
Serial ATA; Physical layer; PLL; OOB;
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  • Reference
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