• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8B
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• pp.609-614
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• 2008

Upstream data frame of TDM-PON includes various types of overheads, and there exist guard bands between consecutive frames from different ONUs. Although they are indispensible in synchronization and performance, they cause bandwidth waste at the same time. To solve this problem, a new TDM-PON that uses two types of wavelengths in upstream transmission is suggested. By even distribution of two wavelengths among ONUs and overhead overlap between frames that use different wavelengths, almost 100% bandwidth efficiency could be achieved. A serializer that multiplexes signals from two wavelengths is implemented for this purpose.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.304-308
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• 2009

This paper presents the deadline driven CPU-Power management scheme for the Real-Time Embedded OS: named TMO-eCos. It used the scheduling scenarios generated by a task serialization technique for hard real- time TMO system. The serializer does a off-line analysis at design time with period, deadline and WCET of periodic tasks. Finally, TMO-eCos kernel controls the CPU speed to save the power consumption under the condition that periodic tasks do not violate deadlines. As a result, the system shows a reasonable amount of power saving. This paper presents all of these processes and test results.

• The KIPS Transactions:PartD
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• v.12D no.6 s.102
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• pp.881-888
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• 2005

As the internet continues to grow, the quantity of information on the Web increases beyond measure. The internet users' abilities and requirements to use information also become varied and complicated. Ontology can describe correct meaning of web resource and relationships between web resources. And it can extract conformable information that a user wants. Accordingly, we need the ontology to represent knowledge. W3C announced OWL(Web Ontology Language), a meaning description technology for such web resources. But, the development of a professional use of tools that can compose and edit effectively is not yet developed adequately. In this paper, we design and implement an Ontology editor which generates and edits OWL documents through intuitional interface, with a OWL parser, a Internal DataModel, and a Serializer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.167-174
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• 2012

The circuits including with Optical transceiver and clock data recovery, in this paper, SERDES (SERializer-DESerializer) are implemented to construct a GE-PON burst-mode transceiver supporting IEEE 802.3ah and a jig for measuring the burst-mode characteristics, that is to say, PON upstream optical transmission environment are manufactured to evaluate the performance of transceiver. we verified that the limiting amplifier compensated the gap of max. 26dB optical power by experiments. The startup acquisition lock time is 670ns in case of using VSC7123 and 2300ns in case of S2060 and the data acquisition lock time were measured to be 400ns and 600ns, respectively, in the upstream channel transmission in this work. While on the other, VSC7123 is satisfied with IEEE802.3ah recommendations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.37-43
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• 2010

As the speed of A/V streaming, the transmission-speed requirement of serial link is continuously increasing. Consequently, commercial standards, which are released previously, are increasing transmission speed in their newly-updated versions. The flexibility between previous and updated versions is very important requirement, therefore, the transceiver which can operates at more than one data rate is important market demand. This paper demonstrates 4-channel 3.2/ 6.4 Gbps transmitter, which is capable of selecting 1, 1.5, 2, and 3 times of pre-emphasis and 200, 300, 400, and 600 mVdiff,p2p of output swing. The prototype chip was fabricated using $0.13{\mu}m$ CMOS process. Its performances are verified on PCB using COB packaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.