• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1179-1180
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• 2008

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.

• 한국자동차공학회논문집
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• 제8권3호
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• pp.163-170
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• 2000

Accident statistics shows that the portion of fatal occupant injuries due to side impacts is considerably high. The side impact usually leads to a severe intrusion of side structure into the passenger compartment. Furthermore, the safety zone for the side impact is relatively small compared to the front impact. Those kinds of physics for side impact frequently result in a fatal injury for the occupant. Therefore, NHTSA and EEVC are trying to intensify the regulation for the occupant protection against side impact. Both the regulation and recent market trends are asking for an installation of side airbag. There are several types of system configuration for side impact sensing. In this paper, we adopt the acceleration-based remote sensing method for the side airbag control system. We mainly focus on the development of hardware and crash discrimination algorithm of remote sensing unit. The crash discrimination algorithm needs fast decision of airbag firing especially for high-speed side impact such as FMVSS 214 and EEVC tests. It is also required to distinguish between low-speed fire and no-fire events. The algorithm should have a sufficient safety margin against any misuse situation such as hammer blow, door slam, etc. This paper introduces several firing criteria such as acceleration. velocity and energy criteria that use physical value proportional to crash severity. We have made a simulation program by using Matlab/Simulink to implement the proposed algorithm. We have conducted an algorithm calibration by using real crash data for 2,500cc vehicle. The crash performance obtained by the simulation was verified through a pulse injection method. It turned out that the results satisfied the system requirements well.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• 한국정보통신학회논문지
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• 제18권7호
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• pp.1657-1662
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• 2014

본 연구에서는 다중게이트 구조인 n-채널 무접합(junctionless) MuGFET 의 기판 전압이 zero capacitor RAM(Z-RAM) 특성에 미치는 영향에 대하여 실험적으로 분석하였다. 핀 폭이 50nm 이고, 핀 수가 1인 무접합 트랜지스터의 드레인에 3.5V, 기판에 0V 가 인가된 경우, 메모리 윈도우는 0.34V 이며 센싱 마진 은 $1.8{\times}10^4$ 의 특성을 보였다. 양의 기판 전압이 인가되면 충격 이온화가 증가하여 메모리 윈도우와 센싱 마진 특성이 개선되었다. 기판 전압이 0V에서 10V로 증가함에 따라, 메모리 윈도우 값은 0.34V 에서 0.96V 로 증가하였고, 센싱 마진 또한 소폭 증가하였다. 기판 전압에 따른 무접합 트랜지스터의 메모리 윈도우 민감도가 반전 모드 트랜지스터 보다 큰 것을 알 수 있었다. Gate Induced Drain Leakage(GIDL) 전류가 작은 무접합 소자의 경우 반전모드 소자에 비해서 보유시간 특성이 좋을 것으로 사료된다. Z-RAM의 동작 신뢰도 평가를 위해서 셋/리셋 전압 및 전류의 변화를 측정하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.363-369
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• 2017

Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.110-116
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• 2004

We propose a novel sensing scheme, which operates by sensing the difference in voltage between a memory cell and a reference cell for a magneto-resistive random access memory (MRAM). A new midpoint-reference generation circuit is adopted for the reference cell to improve the sensing margin and to guarantee correct operation of sensing circuit for wide range of tunnel magneto resistance (TMR) voltages. In this scheme, the output voltage of the reference cell becomes nearly the midpoint between the cell voltages of high and low states even if the voltage across the magnetic tunnel junction (MTJ) varies.

• Nuclear Engineering and Technology
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• 제55권5호
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• pp.1533-1540
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• 2023

Self-Powered Neutron Detectors(SPNDs) are used to calculate core power distributions, an essential factor in the safe operation of nuclear power plants. Some detectors may fail during normal operation, and signals from failed detectors are isolated from intact signals. The calculated detailed power distribution accuracy depends on the number of available detector signals. Failed detectors decrease the operating margin by enlarging the power distribution measurement error. Therefore, a thorough reconstruction of the failed detector signals is critical. This note suggests a compressive sensing based methodology that rationally reconstructs the readings of failed detectors. The methodology significantly improves reconstruction accuracy by sorting signals and removing high-frequency components from conventional compressive sensing methodology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.264-264
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• 2011

1T-1C로 구성되는 기존의 dynamic random access memory (DRAM)는 데이터를 저장하기 위해 적절한 커패시턴스를 확보해야 한다. 따라서 커패시터 면적으로 인한 집적도의 한계에 직면해있으며, 이를 대체하기 위한 새로운 DRAM인 1T- DRAM이 연구되고 있다. 기존의 DRAM과 달리 silicon-on-insulator (SOI) 기술을 이용한 1T-DRAM은 데이터 저장을 위한 커패시터가 요구되지 않는다. 정공을 채널의 중성영역에 축적함으로서 발생하는 포텐셜 변화를 이용하며, 이때 발생하는 드레인 전류차를 이용하여 '0'과 '1'을 구분한다. 기존의 완전공핍형 평면구조의 1T-DRAM은 소스 및 드레인 접합부분에서 발생하는 누설전류로 인해 '0' 상태의 메모리 유지특성이 열화되는 단점을 가지고 있다. 따라서 메모리의 보존특성을 향상시키기 위해 소스/드레인 접합영역을 줄여 누설전류를 감소시키는 구조를 갖는 1T-DRAM의 연구가 필요하다. 또한 고유전율을 가지는 Si3N4를 이용한 oxide-nitride-oxide (ONO)구조의 게이트 절연막을 이용하면 동일한 두께에서 더 낮은 equivalent oxide thickness (EOT)를 얻을 수 있기 때문에 보다 저 전압에서 1T-DRAM 동작이 가능하여 기존의 SiO2 단일층을 이용한 1T-DRAM보다 동일 전압에서 더 큰 sensing margin을 확보할 수 있다. 본 연구에서는 누설전류를 감소시키기 위하여 소스 및 드레인이 채널위로 올려진 recessed channel 구조에 ONO 게이트 절연막을 적용한 1T-DRAM을 제작 및 평가하고, 본 구조의 1T-DRAM적용 가능성 및 ONO구조의 게이트 절연막을 이용한 sensing margin 개선을 확인하였다.