• 한국시뮬레이션학회논문지
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• 제11권3호
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• pp.59-65
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• 2002

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. Project executed that use conveyor in bay semiconductor A line. But conveyor capability is lacking and rundown happened in equipment. Do design without normal simulation and conveyor system failed. The comparison is peformed through simulation using .AutoMod a window 98 based discrete system simulation software, as a tool for comparing performance of proposed layouts. In this research estimate optimum conveyor capability, there is the purpose.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• Nuclear Engineering and Technology
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• 제53권6호
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• pp.1947-1954
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• 2021

In the nuclear medicine imaging, quality control (QC) process using quadrant bar phantom is fundamental aspect of evaluating the spatial resolution. In addition, QC process of gamma camera is performed by daily or weekly. Recently, Monte Carlo simulation using the Geant4 application for tomographic emission (GATE) is widely applied in the pre-clinical nuclear medicine field for modeling gamma cameras with pixelated cadmium telluride (CdTe) semiconductor detector. In this study, we modeled a pixelated CdTe semiconductor detector and quadrant bar phantom (0.5, 1.0, 1.5, and 2.0 mm bar thicknesses) using the GATE tool. Similarity analysis based on correlation coefficients and peak signal-to-noise ratios was performed to compare image qualities for various source to collimator distances (0, 2, 4, 6, and 8 cm) and collimator lengths (0.2, 0.4, 0.6, 0.8, and 1.0 cm). To this end, we selected reference images based on collimator length and source to collimator distance settings. The results demonstrate that as the collimator length increases and the source to collimator distance decreases, the similarity to reference images improves. Therefore, our simulation results represent valuable information for the modeling of CdTe-based semiconductor gamma imaging systems and QC phantoms in the field of nuclear medicine.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.133-140
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• 2004

The origin of the phenomena, obstructing circuit performance in the RF operating regime, as well as their modeling will be discussed. The applied surface-potential-based modeling allows self-consistent description of all phenomena important for accurate circuit simulation, as demonstrated with the MOSFET model HiSIM.

• 한국시뮬레이션학회논문지
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• 제15권2호
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• pp.51-57
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• 2006

현재 반도체 산업은 200mm 웨이퍼에서 300mm 웨이퍼 공정으로 기술이 변화하고 있다. 300mm 웨이퍼 제조업체들은 Fabrication Line (FAB Line) 자동화를 비용절감 실현의 방책으로 사용하고 있다. 또한 기술의 확산, 시장 경쟁력의 격화 등으로 생산성 향상에 의한 원가절감이 반도체 산업 성장의 근본요인이 되고 있다. 대부분의 반도체 업체들은 생산성을 높이기 위해 average cycle time을 줄이는데 총력을 기울이고 있다. 본 논문에서는 average cycle time을 줄이는 데 중점을 두고, 300mm 반도체 제조공정을 시뮬레이션 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• 전기전자학회논문지
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• 제18권3호
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• pp.341-348
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• 2014

재사용하고자 하는 다수의 반도체 IP를 연결하여 통합 칩을 구현하는 경우, 각각의 반도체 IP에 대해 합성이 가능한 코드 파일과 시뮬레이션 및 검증이 가능한 인터페이스 모델링 파일을 제공하여야 한다. 그러나 이들 반도체 IP의 설계자가 모두 다르기 때문에 인터페이스 모델링 파일의 기술 방법 및 구체도 수준이 제각각이어서 시뮬레이션 및 검증이 어렵다는 문제가 있다. 본 논문에서는 반도체 IP 인터페이스의 모델링을 몇 가지 정의된 구체도 수준으로 제한하여 표준화한 모델링 방법을 제안한다. 제안된 방법은 통합 칩 설계자가 서로 다른 반도체 IP를 손쉽게 연결하여 시뮬레이션하고 검증하는데 도움이 된다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.651-652
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• 2013

• 산업공학
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• 제19권2호
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• pp.97-105
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• 2006

In this paper, based on the process analysis of a semiconductor company, a lot order release procedure (input regulation) is developed for a semiconductor company. The major characteristic of the order release procedure in this paper is to consider the workloads of machines which are obtained from a virtual lot flows by the dispatching rule at machines in the shop of the semiconductor company. The objective is to minimize the cycle time and to obtain other good performances. A simulation is performed in order to evaluate the order release procedure in this paper.