• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.99.4-99
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• 1998

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.98.1-98
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• 1998

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.25-33
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• 2007

A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process, which is named SCNU-EBL, has been developed for semiconductor nanometer pattern design and fabrication. The simulator is composed of a MC simulation model of electron trajectory into solid targets, an Gaussian-beam exposure simulation model, and a development simulation model of photoresist using a string model. Especially for the trajectories of incident electrons into the solid targets, the inner-shell electron scattering of an target atom and its discrete energy loss with an incident electron is efficiently modeled for multi-layer resists and heterogeneous multi-layer targets. The simulator was newly applied to the development profile simulation of ZEP520 positive photoresist for NGL(Next-Generation Lithography). The simulation of ZEP520 for electron-beam nanolithography gave a reasonable agreement with the SEM experiments of ZEP520 photoresist.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.353-356
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• 2004

This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.115-121
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• 2002

The growth of semiconductor industry attracted to researchers like design, facility technique and making small size chip areas. But nowadays, cause of technology extension and oversupply and price down, yield improvement is the most important point on growth. This paper describes the computer mode]ing technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process and to build advanced manufacturing environments. The computer models are built referring an existing 8' wafer production line in Korea.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.41-44
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• 2002

The Semiconductor Industrial are developed after 1940. It was called “Rice of Industrial”. It needs great effect in Electronics. It was developed highly in recent several years with semiconductor manufacturing equipments. Semiconductor manufacturing devices are developed “In-line” type in the first stage. But It was non-effective in modem many type process. Because this reason, Cluster type manufacturing equipments are proposed. Cluster have ability of many-type-process and effective-scheduling by circular type process chamber In this paper. we propose a real-time 3D monitoring and simulation of this semiconductor manufacturing equipments. By proposed monitoring method, we have capability real visual maintanance & virtual simulation. This effective visual 3D monitoring could apply another dangerous environment in entire industrial.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.8
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• pp.3319-3325
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• 2012

This paper describes the development of the TrackSim, which is a discrete event simulation tool for photolithography equipment of semiconductor industry. The TrackSim is focused on the accurate simulation model of the photolithography equipment and easy-to-use user interfaces. TrackSim provides 3D simulation environment for evaluating, validating, and scheduling the photolithography process. One of the major characteristics of TrackSim is in that it is developed based on Applied Materials' AutoMod, a discrete event simulation software broadly used in semiconductor industry. Accordingly, the photolithography model of TrackSim can be used to perform simulation connected with other simulation models built with AutoMod.

• IE interfaces
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• v.18 no.1
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• pp.22-34
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• 2005

This paper introduces a simulation model which is based on the process analysis of a semiconductor company. The objective of the simulation modelis not only to estimate the overall performancesof the company but also to evaluate the performances of various operation rules for shop floor control. First, in order to develop the simulation model, a time study is performed for each process after analyzing the processes for the company. Second, by using ARENA, a simulation model is constructed based on the process analysis and the time study. After the simulation model is tested and run, its results are discussed.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.