• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.99.4-99
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• 1998

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.98.1-98
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• 1998

• 반도체디스플레이기술학회지
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• 제6권3호
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• pp.25-33
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• 2007

A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process, which is named SCNU-EBL, has been developed for semiconductor nanometer pattern design and fabrication. The simulator is composed of a MC simulation model of electron trajectory into solid targets, an Gaussian-beam exposure simulation model, and a development simulation model of photoresist using a string model. Especially for the trajectories of incident electrons into the solid targets, the inner-shell electron scattering of an target atom and its discrete energy loss with an incident electron is efficiently modeled for multi-layer resists and heterogeneous multi-layer targets. The simulator was newly applied to the development profile simulation of ZEP520 positive photoresist for NGL(Next-Generation Lithography). The simulation of ZEP520 for electron-beam nanolithography gave a reasonable agreement with the SEM experiments of ZEP520 photoresist.

• 한국시뮬레이션학회논문지
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• 제8권3호
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.353-356
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• 2004

This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2002년도 추계학술대회 논문집
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• pp.115-121
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• 2002

The growth of semiconductor industry attracted to researchers like design, facility technique and making small size chip areas. But nowadays, cause of technology extension and oversupply and price down, yield improvement is the most important point on growth. This paper describes the computer mode]ing technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process and to build advanced manufacturing environments. The computer models are built referring an existing 8' wafer production line in Korea.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.41-44
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• 2002

The Semiconductor Industrial are developed after 1940. It was called “Rice of Industrial”. It needs great effect in Electronics. It was developed highly in recent several years with semiconductor manufacturing equipments. Semiconductor manufacturing devices are developed “In-line” type in the first stage. But It was non-effective in modem many type process. Because this reason, Cluster type manufacturing equipments are proposed. Cluster have ability of many-type-process and effective-scheduling by circular type process chamber In this paper. we propose a real-time 3D monitoring and simulation of this semiconductor manufacturing equipments. By proposed monitoring method, we have capability real visual maintanance & virtual simulation. This effective visual 3D monitoring could apply another dangerous environment in entire industrial.

• 한국산학기술학회논문지
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• 제13권8호
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• pp.3319-3325
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• 2012

본 논문은 반도체 포토장비의 이산 이벤트 시뮬레이터인 TrackSim의 개발에 관한 것이다. TrackSim은 포토 장비의 시뮬레이션 엔진과 사용하기 쉬운 사용자 환경을 포함하는 시뮬레이터로, 다양한 프로세스 모듈의 구성 및 운영 방법을 효율적으로 평가, 검증, 스케쥴링할 수 있는 3차원 시뮬레이션 환경을 제공한다. TrackSim은 반도체 산업에서 많이 사용되는 이산 사건 시뮬레이션 소프트웨어인 AutoMod를 기반으로 개발되어 시뮬레이션 신뢰성이 보장되며, AutoMod로 개발된 반도체 제조라인 시뮬레이션 모델 속에 함께 연동하여 사용이 가능하다는 특징이 있다.

• 산업공학
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• 제18권1호
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• pp.22-34
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• 2005

This paper introduces a simulation model which is based on the process analysis of a semiconductor company. The objective of the simulation modelis not only to estimate the overall performancesof the company but also to evaluate the performances of various operation rules for shop floor control. First, in order to develop the simulation model, a time study is performed for each process after analyzing the processes for the company. Second, by using ARENA, a simulation model is constructed based on the process analysis and the time study. After the simulation model is tested and run, its results are discussed.

• 한국시뮬레이션학회논문지
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• 제18권4호
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• pp.219-225
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• 2009

본 연구는 복잡하고 다양한 반도체 웨이퍼 가공(FAB) 공정의 전체적인 흐름을 컴퓨터 모델로 구축하고 이를 Device 단면도를 나타내는 프리젠테이션 툴과 연동시키는 교육 모델의 개발을 목적으로 하였다. 급변하는 세계 반도체 시장에서 국내 반도체 업체는 지속적인 기술 개발과 더불어 효율적인 생산관리에 대응할 수 있도록 하여 국제 경쟁력을 키워야 할 것이다. 따라서 본 연구에서 다루어진 공정의 흐름과 각 단위공정의 특성을 바탕으로 설립된 모델은 서울대학교 반도체 공동 연구소를 대상으로 구현되었으나 앞으로 생산 관리를 담당할 국내 반도체 업체들의 신입사원과 현장기술자의 질적 향상을 위한 시청각 교육용 자료로의 활용 시 상당한 효과를 거둘 것이라 예상된다. 이는 생산업체에 국한되어지는 것만은 아니며 반도체 공정에 관련된 대학 학과목에서도 활용되어지리라 생각된다. 또한 확장성과변화에 유연한 모델을 개발함으로써 반도체 생산 업체들은 구성된 표준 모델을 이용하여 각 회사의 실정에 맞추어 자사에 대한 시뮬레이션을 손쉽게 수행함으로써 많은 교육 효과와 이에 따른 원가 절감의 효과까지 거둘 수 있을 것이다.